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| tms320f2810, tms320f2811, tms320f2812 tms320c2810, tms320c2811, tms320c2812 digital signal processors data manual literature number: sprs174l april 2001 ? revised december 2004
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2004, texas instruments incorporated revision history 3 april 2001 ? revised june 2004 sprs174k revision history this data sheet revision history highlights the technical changes made to the sprs174k device-specific data sheet to make it an sprs174l revision. global change: added the zhh package page no. additions/changes/deletions 15 changed notes on table 2?1 15 added the zhh package to table 2?1 and changed the product status from tmx to tms 16 added the zhh package to section 2.3 19 added a line to the description of xclkout in table 2?2 37 added new table 3?4, boot mode selection 47 modified the note on interrupts in table 3?11 64 modified the equation in section 4.3 75 changed pcr1 to pcr in table 4?7 85 modified figure 4?12 and changed title from ?modes of operation? to ?gpio/peripheral pin multiplexing? 87 added zhh package to figure 5?1 87 updated section 5.2, documentation support 92 added a new row and two footnotes to the electrical characterisitcs over recommended operating conditions table (section 6.3) 92 added vdd1 to the first footnote of the current consumption by power-supply pins over recommended operating conditions during low-power modes at 150-mhz sysclkout (tms320f281x) table (section 6.4) 93 added new values to the current consumption by power-suply pins over recommended operating cnditions during low-power modes at 150-mhz sysclkout (tms320c281x) (section 6.5) 94?95 added figure 6?1?through figure 6?4 107 added table 6?10 as part of splitting idle mode timing requirements and switiching characteristics into two separate tables 107 added table 6?12 as part of splitting standby mode timing requirements and switiching characteristics into two separate tables 108 added table 6?14 as part of splitting halt mode timing requirements and switiching characteristics into two separate tables 153 added new table 6?60 rom access timing 153 added new table 6?61 minimum required wait-states at different frequencies (c281x devices) 154 added section 6.33 migrating from f281x to c281x devices 4 april 2001 ? revised june 2004 sprs174k this page is intentionally left blank. contents 5 april 2001 ? revised december 2004 sprs174l contents section page 1 features 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 description 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 device summary 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 pin assignments 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 terminal assignments for the ghh package 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 pin assignments for the pgf package 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.3 pin assignments for the pbk package 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 signal descriptions 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 functional overview 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 memory map 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 brief descriptions 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 c28x cpu 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 memory bus (harvard bus architecture) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 peripheral bus 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 real-time jtag and analysis 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 external interface (xintf) (2812 only) 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 flash (f281x only) 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.7 rom (c281x only) 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.8 m0, m1 sarams 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.9 l0, l1, h0 sarams 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.10 boot rom 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.11 security 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.12 peripheral interrupt expansion (pie) block 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.13 external interrupts (xint1, xint2, xint13, xnmi) 38 . . . . . . . . . . . . . . . . . . . . . . . 3.2.14 oscillator and pll 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.15 watchdog 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.16 peripheral clocking 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.17 low-power modes 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.18 peripheral frames 0, 1, 2 (pfn) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.19 general-purpose input/output (gpio) multiplexer 39 . . . . . . . . . . . . . . . . . . . . . . . . 3.2.20 32-bit cpu-timers (0, 1, 2) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.21 control peripherals 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.22 serial port peripherals 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 register map 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 device emulation registers 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 external interface, xintf (2812 only) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 timing registers 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 xrevision register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 interrupts 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 external interrupts 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 system control 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 osc and pll block 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8.1 loss of input clock 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 pll-based clock module 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 external reference oscillator clock option 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 watchdog block 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents 6 april 2001 ? revised december 2004 sprs174l 3.12 low-power modes block 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 peripherals 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 32-bit cpu-timers 0/1/2 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 event manager modules (eva, evb) 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 general-purpose (gp) timers 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 full-compare units 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 programmable deadband generator 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 pwm waveform generation 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 double update pwm mode 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 pwm characteristics 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 capture unit 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.8 quadrature-encoder pulse (qep) circuit 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.9 external adc start-of-conversion 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 enhanced analog-to-digital converter (adc) module 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 enhanced controller area network (ecan) module 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 multichannel buffered serial port (mcbsp) module 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 serial communications interface (sci) module 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 serial peripheral interface (spi) module 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 gpio mux 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 development support 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 device and development support tool nomenclature 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 documentation support 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 absolute maximum ratings 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 recommended operating conditions? 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 electrical characteristics over recommended operating conditions (unless otherwise noted) 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 current consumption by power-supply pins over recommended operating conditions during low-power modes at 150-mhz sysclkout (tms320f281x) 92 . . . . . . . . . . . . . . . . . . 6.5 current consumption by power-supply pins over recommended operating conditions during low-power modes at 150-mhz sysclkout (tms320c281x) 93 . . . . . . . . . . . . . . . . . . 6.6 current consumption graphs 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 reducing current consumption 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 power sequencing requirements 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 signal transition levels 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 timing parameter symbology 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 general notes on timing parameters 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 test load circuit 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 device clock table 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 clock requirements and characteristics 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.1 input clock requirements 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.2 output clock characteristics 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 reset timing 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 low-power mode wakeup timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 event manager interface 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.1 pwm timing 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.2 interrupt timing 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 general-purpose input/output (gpio) ? output timing 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 general-purpose input/output (gpio) ? input timing 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 spi master mode timing 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 spi slave mode timing 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents 7 april 2001 ? revised december 2004 sprs174l 6.22 external interface (xintf) timing 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.23 xintf signal alignment to xclkout 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.24 external interface read timing 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.25 external interface write timing 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.26 external interface ready-on-read timing with one external wait state 128 . . . . . . . . . . . . . . . . 6.27 external interface ready-on-write timing with one external wait state 131 . . . . . . . . . . . . . . . . 6.28 xhold and xholda 134 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.29 xhold /xholda timing 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30 on-chip analog-to-digital converter 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.1 adc absolute maximum ratings? 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.2 adc electrical characteristics over recommended operating conditions 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.3 current consumption for different adc configurations (at 25-mhz adcclk) 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.4 adc power-up control bit timing 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.5 detailed description 141 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.30.6 sequential sampling mode (single-channel) (smode = 0) 141 . . . . . . . . . . . . . . . 6.30.7 simultaneous sampling mode (dual-channel) (smode = 1) 143 . . . . . . . . . . . . . . 6.30.8 definitions of specifications and terminology 144 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31 multichannel buffered serial port (mcbsp) timing 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.1 mcbsp transmit and receive timing 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.31.2 mcbsp as spi master or slave timing 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32 flash timing (f281x only) 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.32.1 recommended operating conditions 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.33 migrating from f281x devices to c281x devices 154 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mechanical data 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures 8 april 2001 ? revised december 2004 sprs174l list of figures figure page 2?1. tms320f2812 and tms320c2812 179-ball ghh microstar bga (bottom view) 16 . . . . . . . . . . . . . . . . . . . 2?2. tms320f2812 and tms320c2812 176-pin pgf lqfp (top view) 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?3. tms320f2810, tms320f2811, tms320c2810, and tms320c2811 128-pin pbk lqfp (top view) 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1. functional block diagram 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2. f2812/c2812 memory map 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3. f2811/c2811 memory map 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4. f2810/c2810 memory map 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5. external interface block diagram 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6. interrupt sources 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7. multiplexing of interrupts using the pie block 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8. clock and reset domains 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9. osc and pll block 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10. recommended crystal/ clock connection 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11. watchdog module 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1. cpu-timers 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2. cpu-timer interrupts signals and output signal 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3. event manager a functional block diagram 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4. block diagram of the f281x and c281x adc module 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5. adc pin connections with internal reference 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?6. adc pin connections with external reference 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?7. ecan block diagram and interface circuit 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8. ecan memory map 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9. mcbsp module with fifo 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?10. serial communications interface (sci) module block diagram 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?11. serial peripheral interface module block diagram (slave mode) 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?12. gpio/peripheral pin multiplexing 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5?1. tms320x28x device nomenclature 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1. f2812/f2811/f2810 typical current consumption over frequency 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2. f2812/f2811/f2810 typical power consumption over frequency 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?3. c2812/c2811/c2810 typical current consumption over frequency 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?4. c2812/c2811/c2810 typical power consumption over frequency 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?5. f2812/f2811/f2810 typical power-up and power-down sequence ? option 2 97 . . . . . . . . . . . . . . . . . . . . . 6?6. output levels 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?7. input levels 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?8. 3.3-v test load circuit 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?9. clock timing 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?10. power-on reset in microcomputer mode (xmp/mc = 0) 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?11. power-on reset in microprocessor mode (xmp/mc = 1) 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?12. warm reset in microcomputer mode 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?13. effect of writing into pllcr register 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures 9 april 2001 ? revised december 2004 sprs174l 6?14. idle entry and exit timing 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?15. standby entry and exit timing 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?16. halt wakeup using xnmi 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?17. pwm output timing 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?18. tdirx timing 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?19. evasoc timing 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?20. evbsoc timing 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?21. external interrupt timing 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22. general-purpose output timing 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23. gpio input qualifier ? example diagram for qualprd = 1 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?24. general-purpose input timing 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?25. spi master mode external timing (clock phase = 0) 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?26. spi master external timing (clock phase = 1) 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?27. spi slave mode external timing (clock phase = 0) 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?28. spi slave mode external timing (clock phase = 1) 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?29. relationship between xtimclk and sysclkout 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?30. example read access 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?31. example write access 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?32. example read with synchronous xready access 129 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?33. example read with asynchronous xready access 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?34. write with synchronous xready access 132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?35. write with asynchronous xready access 133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?36. external interface hold waveform 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?37. xhold /xholda timing requirements (xclkout = 1/2 xtimclk) 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?38. adc analog input impedance model 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?39. adc power-up control bit timing 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?40. sequential sampling mode (single-channel) timing 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?41. simultaneous sampling mode timing 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?42. mcbsp receive timing 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?43. mcbsp transmit timing 147 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?44. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?45. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 149 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?46. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 150 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?47. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables 10 april 2001 ? revised december 2004 sprs174l list of tables table page 2?1. hardware features 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?2. signal descriptions 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?1. addresses of flash sectors in f2812 and f2811 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?2. addresses of flash sectors in f2810 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?3. wait states 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?4. boot mode selection 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?5. peripheral frame 0 registers 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?6. peripheral frame 1 registers 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?7. peripheral frame 2 registers 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?8. device emulation registers 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?9. xintf configuration and control register mappings 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?10. xrevision register bit definitions 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?11. pie peripheral interrupts 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?12. pie configuration and control registers 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?13. external interrupts registers 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?14. pll, clocking, watchdog, and low-power mode registers 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?15. pllcr register bit definitions 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?16. possible pll configuration modes 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3?17. f281x and c281x low-power modes 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?1. cpu-timers 0, 1, 2 configuration and control registers 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?2. module and signal names for eva and evb 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?3. eva registers 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?4. adc registers 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?5. 3.3-v ecan transceivers for the tms320f281x and tms320c281x dsps 70 . . . . . . . . . . . . . . . . . . . . . . . . 4?6. can registers map 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?7. mcbsp register summary 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?8. sci-a registers 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?9. sci-b registers 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?10. spi registers 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?11. gpio mux registers 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4?12. gpio data registers 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?1. typical current consumption by various peripherals (at 150 mhz) 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?2. recommended ?low-dropout regulators? 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?3. tms320f281x and tms320c281x clock table and nomenclature 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?4. input clock frequency 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?5. xclkin timing requirements ? pll bypassed or enabled 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?6. xclkin timing requirements ? pll disabled 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?7. possible pll configuration modes 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?8. xclkout switching characteristics (pll bypassed or enabled) 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?9. reset (xrs) timing requirements 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?10. idle mode timing requirements 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?11. idle mode switching characteristics 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?12. standby mode timing requirements 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?13. standby mode switching characteristics 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?14. halt mode timing requirements 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?15. halt mode switching characteristics 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables 11 april 2001 ? revised december 2004 sprs174l 6?16. pwm switching characteristics 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?17. timer and capture unit timing requirements 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?18. external adc start-of-conversion ? eva ? switching characteristics 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?19. external adc start-of-conversion ? evb ? switching characteristics 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?20. interrupt switching characteristics 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?21. interrupt timing requirements 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?22. general-purpose output switching characteristics 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?23. general-purpose input timing requirements 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?24. spi master mode external timing (clock phase = 0) 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?25. spi master mode external timing (clock phase = 1) 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?26. spi slave mode external timing (clock phase = 0) 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?27. spi slave mode external timing (clock phase = 1) 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?28. relationship between parameters configured in xtiming and duration of pulse 122 . . . . . . . . . . . . . . . . . 6?29. xintf clock configurations 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?30. external memory interface read switching characteristics 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?31. external memory interface read timing requirements 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?32. external memory interface write switching characteristics 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?33. external memory interface read switching characteristics (ready-on-read, 1 wait state) 128 . . . . . . . . . 6?34. external memory interface read timing requirements (ready-on-read, 1 wait state) 128 . . . . . . . . . . . . 6?35. synchronous xready timing requirements (ready-on-read, 1 wait state) 128 . . . . . . . . . . . . . . . . . . . . . 6?36. asynchronous xready timing requirements (ready-on-read, 1 wait state) 128 . . . . . . . . . . . . . . . . . . . . 6?37. external memory interface write switching characteristics (ready-on-write, 1 wait state) 131 . . . . . . . . 6?38. synchronous xready timing requirements (ready-on-write, 1 wait state) 131 . . . . . . . . . . . . . . . . . . . . . 6?39. asynchronous xready timing requirements (ready-on-write, 1 wait state) 131 . . . . . . . . . . . . . . . . . . . . 6?40. xhold /xholda timing requirements (xclkout = xtimclk) 135 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?41. xhold /xholda timing requirements (xclkout = 1/2 xtimclk) 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?42. dc specifications 138 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?43. ac specifications 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?44. adc power-up delays 140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?45. sequential sampling mode timing 142 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?46. simultaneous sampling mode timing 143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?47. mcbsp timing requirements 145 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?48. mcbsp switching characteristics 146 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?49. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0) 148 . . . . . . . . . . . . . . . 6?50. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 0) 148 . . . . . . . . . . . 6?51. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0) 149 . . . . . . . . . . . . . . . 6?52. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 0) 149 . . . . . . . . . . . 6?53. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1) 150 . . . . . . . . . . . . . . . 6?54. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 1) 150 . . . . . . . . . . . 6?55. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1) 151 . . . . . . . . . . . . . . . 6?56. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 1) 151 . . . . . . . . . . . 6?57. flash parameters at 150-mhz sysclkout 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?58. flash/otp access timing 152 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?59. minimum required wait-states at different frequencies (f281x devices) 152 . . . . . . . . . . . . . . . . . . . . . . . . 6?60. rom access timing 153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6?61. minimum required wait-states at different frequencies (c281x devices) 153 . . . . . . . . . . . . . . . . . . . . . . . . 7?1. thermal resistance characteristics for 179-ball ghh 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?2. thermal resistance characteristics for 179-ball zhh 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?3. thermal resistance characteristics for 176-pin pgf 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7?4. thermal resistance characteristics for 128-pin pbk 155 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 april 2001 ? revised december 2004 sprs174l this page is intentionally left blank. features 13 april 2001 ? revised december 2004 sprs174l 1 features high-performance static cmos technology ? 150 mhz (6.67-ns cycle time) ? low-power (1.8-v core @135 mhz, 1.9-v core @150 mhz, 3.3-v i/o) design jtag boundary scan support ? high-performance 32-bit cpu (tms320c28x) ? 16 x 16 and 32 x 32 mac operations ? 16 x 16 dual mac ? harvard bus architecture ? atomic operations ? fast interrupt response and processing ? unified memory programming model ? 4m linear program/data address reach ? code-efficient (in c/c++ and assembly) ? tms320f24x/lf240x processor source code compatible on-chip memory ? flash devices: up to 128k x 16 flash (four 8k x 16 and six 16k x 16 sectors) ? rom devices: up to 128k x 16 rom ? 1k x 16 otp rom ? l0 and l1: 2 blocks of 4k x 16 each single-access ram (saram) ? h0: 1 block of 8k x 16 saram ? m0 and m1: 2 blocks of 1k x 16 each saram boot rom (4k x 16) ? with software boot modes ? standard math tables external interface (2812) ? up to 1m total memory ? programmable wait states ? programmable read/write strobe timing ? three individual chip selects clock and system control ? dynamic pll ratio changes supported ? on-chip oscillator ? watchdog timer module three external interrupts peripheral interrupt expansion (pie) block that supports 45 peripheral interrupts three 32-bit cpu-timers 128-bit security key/lock ? protects flash/rom/otp and l0/l1 saram ? prevents firmware reverse engineering motor control peripherals ? two event managers (eva, evb) ? compatible to 240xa devices serial port peripherals ? serial peripheral interface (spi) ? two serial communications interfaces (scis), standard uart ? enhanced controller area network (ecan) ? multichannel buffered serial port (mcbsp) 12-bit adc, 16 channels ? 2 x 8 channel input multiplexer ? two sample-and-hold ? single/simultaneous conversions ? fast conversion rate: 80 ns/12.5 msps up to 56 general purpose i/o (gpio) pins advanced emulation features ? analysis and breakpoint functions ? real-time debug via hardware development tools include ? ansi c/c++ compiler/assembler/linker ? code composer studio ? ide ? dsp/bios ? ? jtag scan controllers ? low-power modes and power savings ? idle, standby, halt modes supported ? disable individual peripheral clocks package options ? 179-ball microstar bga ? with external memory interface (ghh), (zhh) (2812) ? 176-pin low-profile quad flatpack (lqfp) with external memory interface (pgf) (2812) ? 128-pin lqfp without external memory interface (pbk) (2810, 2811) temperature options: ? a: ?40 c to 85 c (ghh, zhh, pgf, pbk) ? s/q: ?40 c to 125 c (ghh, zhh, pgf, pbk) tms320c24x, code composer studio, dsp/bios, and microstar bga are trademarks of texas instruments. ? ieee standard 1149.1?1990, ieee standard test-access port introduction 14 april 2001 ? revised december 2004 sprs174l 2 introduction this section provides a summary of each device?s features, lists the pin assignments, and describes the function of each pin. this document also provides detailed descriptions of peripherals, electrical specifications, parameter measurement information, and mechanical data about the available packaging. 2.1 description the tms320f2810, tms320f2811, tms320f2812, tms320c2810, tms320c2811, and tms320c2812 devices, members of the tms320c28x ? dsp generation, are highly integrated, high-performance solutions for demanding control applications. the functional blocks and the memory maps are described in section 3, functional overview. throughout this document, tms320f2810, tms320f2811, and tms320f2812 are abbreviated as f2810, f2811, and f2812, respectively. f281x denotes all three flash devices. tms320c2810, tms320c2811, and tms320c2812 are abbreviated as c2810, c2811, and c2812, respectively. c281x denotes all three rom devices. 2810 denotes both f2810 and c2810 devices; 2811 denotes both f2811 and c2811 devices; and 2812 denotes both f2812 and c2812 devices. tms320c28x is a trademark of texas instruments. all trademarks are the property of their respective owners. introduction 15 april 2001 ? revised december 2004 sprs174l 2.2 device summary table 2?1 provides a summary of each device?s features. table 2?1. hardware features ? feature f2810 f2811 f2812 c2810 c2811 c2812 instruction cycle (at 150 mhz) 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns 6.67 ns single-access ram (saram) (16-bit word) 18k 18k 18k 18k 18k 18k 3.3-v on-chip flash (16-bit word) 64k 128k 128k ? ? ? on-chip rom (16-bit word) ? ? ? 64k 128k 128k code security for on-chip flash/saram/otp/rom yes yes yes yes yes yes boot rom yes yes yes yes yes yes otp rom (1k x 16) yes yes yes yes ? yes ? yes ? external memory interface ? ? yes ? ? yes event managers a and b (eva and evb) eva, evb eva, evb eva, evb eva, evb eva, evb eva, evb general-purpose (gp) timers 4 4 4 4 4 4 compare (cmp)/pwm 16 16 16 16 16 16 capture (cap)/qep channels 6/2 6/2 6/2 6/2 6/2 6/2 watchdog timer yes yes yes yes yes yes 12-bit adc yes yes yes yes yes yes channels 16 16 16 16 16 16 32-bit cpu timers 3 3 3 3 3 3 spi yes yes yes yes yes yes scia, scib scia, scib scia, scib scia, scib scia, scib scia, scib scia, scib can yes yes yes yes yes yes mcbsp yes yes yes yes yes yes digital i/o pins (shared) 56 56 56 56 56 56 external interrupts 3 3 3 3 3 3 supply voltage 1.8-v core, (135 mhz) 1.9-v core (150 mhz), 3.3-v i/o packaging 128-pin pbk 128-pin pbk 179-ball ghh and zhh 176-pin pgf 128-pin pbk 128-pin pbk 179-ball ghh and zhh 176-pin pgf temperature options a: ?40 c to 85 c yes yes yes yes yes yes temperature options s/q: ?40 c to 125 c yes yes yes yes yes yes product status ? tms tms tms tms tms tms ? the tms320f2810, tms320f2811, tms320f2812, tms320c2810, tms320c2811, tms320c2812 digital signal processors silicon errata (literature number sprz193) has been posted on the texas instruments (ti) website. it will be updated as needed. ? on c281x devices, otp is replaced by a 1k x 16 block of rom. the s temperature option has been replaced by the q temperature option (40 c to 125 c) from silicon revision e onwards. q stands for ?40 c to 125 c q100 automotive fault grading. ? see section 5.1, device and development support nomenclature for descriptions of device stages. introduction 16 april 2001 ? revised december 2004 sprs174l 2.3 pin assignments figure 2?1 illustrates the ball locations for the 179-ball ghh and zhh ball grid array (bga) package. figure 2?2 shows the pin assignments for the 176-pin pgf low-profile quad flatpack (lqfp) and figure 2?3 shows the pin assignments for the 128-pin pbk lqfp. table 2?2 describes the function(s) of each pin. 2.3.1 terminal assignments for the ghh package see table 2?2 for a description of each terminal?s function(s). 14 12 13 10 11 89 56 34 12 7 xa[14] xf _xplldis v ssaio adcina0 adcina4 v dda2 v dd1 scirxda xa[16] xd[15] testsel xa[11] adcinb2 v ddaio adclo adcina3 adcina7 xready xa[17] v ss xa[15] v dd xd[14] trst xzcs6and7 v ss adcinb3 adcinb0 adcinb1 adcina2 v ssa2 v ss1 scitxda v dd emu1 v ss xa[12] xa[10] tdi v dd adcinb6 adcinb5 adcinb4 adcina1 adcina6 xrs xa[18] xint1 _xbio v ss emu0 tdo tms xa[9] p m l j h k n g e f d c a b adcrefp xint2 _adcsoc avdd- refbg avss- refbg adcrefm adcina5 adc- bgrefin xhold xnmi _xint13 v ddio xa[13] c2trip xa[8] c1trip v ss xmp/mc adc- resext v ssa1 v dda1 adcinb7 c3trip xclkout xa[7] tclkina tdira mdxa mdra xd[0] v ss xa[0] t2ctrip / evasoc v ddio v dd v ss xa[6] v dd mclkra xd[1] mfsxa xd[2] cap1 _qep1 cap2 _qep2 cap3 _qepi1 xa[5] t1ctrip _pdpinta mclkxa mfsra xd[3] v ddio xd[5] xd[13] t1pwm _t1cmp xa[4] t2pwm _t2cmp v ss v ss spiclka xd[4] spistea t3pwm _t3cmp v ss c6trip tclkinb x1/ xclkin xholda pwm5 v dd v ss pwm6 v dd v ss xd[6] pwm11 xd[7] c5trip v ddio tdirb xd[10] v ddio v ss pwm3 pwm4 xd[12] spisimoa xa[1] xrd pwm12 cap4 _qep3 cap5 _qep4 test1 xd[9] x2 v ss xa[3] pwm1 scirxdb pwm2 spisomia pwm9 xr/w t4pwm _t4cmp c4trip v dd3vfl xd[11] xa[2] xwe cantxa canrxa v ddio xzcs0and1 pwm10 v ss v dd cap6 _qepi2 xd[8] v ss v dd t3ctrip _pdpintb t4ctrip / evbsoc v dd xzcs2 scitxdb tck pwm7 test2 pwm8 figure 2?1. tms320f2812 and tms320c2812 179-ball ghh microstar bga ? (bottom view) introduction 17 april 2001 ? revised december 2004 sprs174l 2.3.2 pin assignments for the pgf package the tms320f2812 and tms320c2812 176-pin pgf low-profile quad flatpack (lqfp) pin assignments are shown in figure 2?2. see table 2?2 for a description of each pin?s function(s). v ddaio 1 133 176 adcinb0 adcinb1 adcinb2 adcinb3 adcinb4 adcinb5 adcinb6 adcinb7 adcrefm adcrefp avssrefbg avddrefbg v dda1 v ssa1 adcresext mc xmp/ xa[0] v ss mdra xd[0] mdxa v dd xd[1] mclkra mfsxa xd[2] mclkxa mfsra xd[3] v ddio v ss xd[4] spiclka spistea xd[5] v dd v ss xd[6] spisimoa spisomia xrd xa[1] xzcs0and1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 xa[11] tdi xa[10] tdo tms xa[9] xa[8] xclkout xa[7] tclkina tdira xa[6] cap3_qepi1 xa[5] cap2_qep2 cap1_qep1 t2pwm_t2cmp xa[4] t1pwm_t1cmp pwm6 pwm5 xd[13] xd[12] pwm4 pwm3 pwm2 pwm1 scirxdb scitxdb canrxa v ss v dd v ss t1ctrip_pdpinta v dd v ss v ddio t2ctrip / evasoc v ss c1trip c2trip c3trip v dd v ss pwm7 pwm8 pwm9 pwm10 pwm11 pwm12 xr/w v ss t3pwm_t3cmp xd[7] t4pwm_t4cmp v dd cap4_qep3 v ss cap5_qep4 cap6_qepi2 c4trip c5trip c6trip v ddio xd[8] test2 test1 xd[9] v dd3vfl v ss tdirb tclkinb xd[10] xd[11] v dd x2 x1/xclkin v ss t3ctrip_pdpintb xa[2] v ddio xholda t4ctrip /evbsoc xwe xa[3] v ss cantxa xzcs2 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 88 45 132 89 44 xzcs6and7 testsel trst tck emu0 xa[12] xd[14] xf_xplldis xa[13] v ss v dd xa[14] v ddio emu1 xd[15] xa[15] xint1_xbio xnmi_xint13 xint2_adcsoc xa[16] v ss v dd scitxda xa[17] scirxda xa[18] xhold xrs xready v dd1 v ss1 adcbgrefin v ssa2 v dda2 adcina7 adcina6 adcina5 adcina4 adcina3 adcina2 adcina1 adcina0 adclo v ssaio figure 2?2. tms320f2812 and tms320c2812 176-pin pgf lqfp (top view) introduction 18 april 2001 ? revised december 2004 sprs174l 2.3.3 pin assignments for the pbk package the tms320f2810, tms320f2811, tms320c2810, and tms320c2811 128-pin pbk low-profile quad flatpack (lqfp) pin assignments are shown in figure 2?3. see table 2?2 for a description of each pin?s function(s). 1 97 96 65 32 128 64 33 v ddaio adcinb0 adcinb1 adcinb2 adcinb3 adcinb4 adcinb5 adcinb6 adcinb7 adcrefm adcrefp avssrefbg avddrefbg v dda1 v ssa1 adcresext v ss mdra mdxa v dd mclkra mfsxa mclkxa mfsra v ddio v ss spiclka spistea v dd v ss spisimoa spisomia 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 tdo tms xclkout tclkina tdira cap1_qep1 t2pwm_t2cmp t1pwm_t1cmp pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 scirxdb scitxdb canrxa v ss v dd cap2_qep2 cap3_qepi1 t1ctrip_pdpinta v dd v ddio t2ctrip/ evasoc v ss c1trip c2trip c3trip v dd v ss tdi pwm7 pwm8 pwm9 pwm10 pwm11 pwm12 t3pwm_t3cmp t4pwm_t4cmp v dd cap4_qep3 cap5_qep4 cap6_qepi2 c4trip c5trip c6trip v ddio test2 test1 v dd3vfl v ss tdirb tclkinb v dd x2 x1/xclkin v ss t3ctrip_pdpintb v ss v dd cantxa 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 39 63 t4ctrip /evbsoc v ss 127 126 125 124 123 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 122 98 testsel trst tck emu0 xf_xplldis v dd v ss v ddio emu1 xint1_xbio xnmi_xint13 xint2_adcsoc v ss v dd scitxda scirxda xrs v dd1 v ss1 adcbgrefin v ssa2 v dda2 adcina7 adcina6 adcina5 adcina4 adcina3 adcina2 adcina1 adcina0 adclo v ssaio figure 2?3. tms320f2810, tms320f2811, tms320c2810, and tms320c2811 128-pin pbk lqfp (top view) introduction 19 april 2001 ? revised december 2004 sprs174l 2.4 signal descriptions table 2?2 specifies the signals on the f281x and c281x devices. all digital inputs are ttl-compatible. all outputs are 3.3 v with cmos levels. inputs are not 5-v tolerant. a 100- a (or 20- a) pullup/pulldown is used. table 2?2. signal descriptions ? pin no. ? name 179-pin ghh 176-pin pgf 128-pin pbk i/o/z ? pu/pd description xintf signals (2812 only) xa[18] d7 158 ? o/z ? xa[17] b7 156 ? o/z ? xa[16] a8 152 ? o/z ? xa[15] b9 148 ? o/z ? xa[14] a10 144 ? o/z ? xa[13] e10 141 ? o/z ? xa[12] c11 138 ? o/z ? xa[11] a14 132 ? o/z xa[10] c12 130 ? o/z ? xa[9] d14 125 ? o/z ? 19-bit xintf address bus xa[8] e12 121 ? o/z ? 19-bit xintf address bus xa[7] f12 118 ? o/z ? xa[6] g14 111 ? o/z ? xa[5] h13 108 ? o/z ? xa[4] j12 103 ? o/z ? xa[3] m11 85 ? o/z ? xa[2] n10 80 ? o/z ? xa[1] m2 43 ? o/z ? xa[0] g5 18 ? o/z xd[15] a9 147 ? i/o/z pu xd[14] b11 139 ? i/o/z pu xd[13] j10 97 ? i/o/z pu xd[12] l14 96 ? i/o/z pu xd[11] n9 74 ? i/o/z pu xd[10] l9 73 ? i/o/z pu xd[9] m8 68 ? i/o/z pu xd[8] p7 65 ? i/o/z pu 16-bit xintf data bus xd[7] l5 54 ? i/o/z pu 16-bit xintf data bus xd[6] l3 39 ? i/o/z pu xd[5] j5 36 ? i/o/z pu xd[4] k3 33 ? i/o/z pu xd[3] j3 30 ? i/o/z pu xd[2] h5 27 ? i/o/z pu xd[1] h3 24 ? i/o/z pu xd[0] g3 21 ? i/o/z pu ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 20 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) name description pu/pd i/o/z ? pin no. name description pu/pd i/o/z ? 128-pin pbk 176-pin pgf 179-pin ghh xintf signals (2812 only) (continued) xmp/mc f1 17 ? i pd microprocessor/microcomputer mode select. switches between microprocessor and microcomputer mode. when high, zone 7 is enabled on the external interface. when low, zone 7 is disabled from the external interface, and on-chip boot rom may be accessed instead. this signal is latched into the xintcnf2 register on a reset and the user can modify this bit in software. the state of the xmp/mc pin is ignored after reset. xhold e7 159 ? i pu external hold request. xhold , when active (low), requests the xintf to release the external bus and place all buses and strobes into a high-impedance state. the xintf will release the bus when any current access is complete and there are no pending accesses on the xintf. xholda k10 82 ? o/z ? external hold acknowledge. xholda is driven active (low) when the xintf has granted a xhold request. all xintf buses and strobe signals will be in a high-impedance state. xholda is released when the xhold signal is released. external devices should only drive the external bus when xholda is active (low). xzcs0and1 p1 44 ? o/z ? xintf zone 0 and zone 1 chip select. xzcs0and1 is active (low) when an access to the xintf zone 0 or zone 1 is performed. xzcs2 p13 88 ? o/z ? xintf zone 2 chip select. xzcs2 is active (low) when an access to the xintf zone 2 is performed. xzcs6and7 b13 133 ? o/z ? xintf zone 6 and zone 7 chip select. xzcs6and7 is active (low) when an access to the xintf zone 6 or zone 7 is performed. xwe n11 84 ? o/z ? write enable. active-low write strobe. the write strobe waveform is specified, per zone basis, by the lead, active, and trail periods in the xtimingx registers. xrd m3 42 ? o/z ? read enable. active-low read strobe. the read strobe waveform is specified, per zone basis, by the lead, active, and trail periods in the xtimingx registers. note: the xrd and xwe signals are mutually exclusive. xr/w n4 51 ? o/z ? read not w rite strobe. normally held high. when low, xr/w indicates write cycle is active; when high, xr/w indicates read cycle is active. ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 21 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) name description pu/pd i/o/z ? pin no. name description pu/pd i/o/z ? 128-pin pbk 176-pin pgf 179-pin ghh xintf signals (2812 only) (continued) xready b6 161 ? i pu ready signal. indicates peripheral is ready to complete the access when asserted to 1. xready can be configured to be a synchronous or an asynchronous input. see the timing diagrams for more details. jtag and miscellaneous signals x1/xclkin k9 77 58 i oscillator input ? input to the internal oscillator. this pin is also used to feed an external clock. the 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the x1/xclkin pin. it should be noted that the x1/xclkin pin is referenced to the 1.8-v (or 1.9-v) core digital power supply (v dd ), rather than the 3.3-v i/o supply (v ddio ). a clamping diode may be used to clamp a buf fered clock signal to ensure that the logic-high level does not exceed v dd (1.8 v or 1.9 v) or a 1.8-v oscillator may be used. x2 m9 76 57 o oscillator output xclkout f11 119 87 o ? output clock derived from sysclkout to be used for external wait-state generation and as a general-purpose clock source. xclkout is either the same frequency, 1/2 the frequency, or 1/4 the frequency of sysclkout. at reset, xclkout = sysclkout/4. the xclkout signal can be turned off by setting bit 3 (clkoff) of the xintcnf2 register to 1. unlike other gpio pins, the xclkout pin is not placed in a high impedance state during reset. testsel a13 134 97 i pd test pin. reserved for ti. must be connected to ground. xrs d6 160 113 i/o pu device reset (in) and watchdog reset (out). device reset. xrs causes the device to terminate execution. the pc will point to the address contained at the location 0x3fffc0. when xrs is brought to a high level, execution begins at the location pointed to by the pc. this pin is driven low by the dsp when a watchdog reset occurs. during watchdog reset, the xrs pin will be driven low for the watchdog reset duration of 512 xclkin cycles. the output buffer of this pin is an open-drain with an internal pullup (100 a, typical). it is recommended that this pin be driven by an open-drain device. test1 m7 67 51 i/o ? test pin. reserved for ti. on f281x devices, test1 must be left unconnected. on c281x devices, this pin is a ?no connect (nc)? (i.e., this pin is not connected to any circuitry internal to the device). test2 n7 66 50 i/o ? test pin. reserved for ti. on f281x devices, test2 must be left unconnected. on c281x devices, this pin is a ?no connect (nc)? (i.e., this pin is not connected to any circuitry internal to the device). ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 22 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) name description pu/pd i/o/z ? pin no. name description pu/pd i/o/z ? 128-pin pbk 176-pin pgf 179-pin ghh jtag trst b12 135 98 i pd jtag test reset with internal pulldown. trst , when driven high, gives the scan system control of the operations of the device. if this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. note: do not use pullup resistors on trst ; it has an internal pulldown device. in a low-noise environment, trst can be left floating. in a high-noise environment, an additional pulldown resistor may be needed. the value of this resistor should be based on drive strength of the debugger pods applicable to the design. a 2.2-k ? resistor generally offers adequate protection. since this is application-specific, it is recommended that each target board is validated for proper operation of the debugger and the application. tck a12 136 99 i pu jtag test clock with internal pullup tms d13 126 92 i pu jtag test-mode select (tms) with internal pullup. this serial control input is clocked into the tap controller on the rising edge of tck. tdi c13 131 96 i pu jtag test data input (tdi) with internal pullup. tdi is clocked into the selected register (instruction or data) on a rising edge of tck. tdo d12 127 93 o/z ? jtag scan out, test data output (tdo). the contents of the selected register (instruction or data) is shifted out of tdo on the falling edge of tck. emu0 d11 137 100 i/o/z pu emulator pin 0. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the jtag scan. emu1 c9 146 105 i/o/z pu emulator pin 1. when trst is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the jtag scan. adc analog input signals adcina7 b5 167 119 i adcina6 d5 168 120 i adcina5 e5 169 121 i 8-channel analog inputs for sample-and-hold a. the adc adcina4 a4 170 122 i 8-channel analog inputs for sample-and-hold a. the adc pins should not be driven before v dda1 , v dda2 , and v ddaio adcina3 b4 171 123 i pins should not be driven before v dda1 , v dda2 , and v ddaio pins have been fully powered up. adcina2 c4 172 124 i pins have been fully powered up. adcina1 d4 173 125 i adcina0 a3 174 126 i ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 23 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) name description pu/pd i/o/z ? pin no. name description pu/pd i/o/z ? 128-pin pbk 176-pin pgf 179-pin ghh adc analog input signals (continued) adcinb7 f5 9 9 i adcinb6 d1 8 8 i adcinb5 d2 7 7 i 8-channel analog inputs for sample-and-hold b. the adc adcinb4 d3 6 6 i 8-channel analog inputs for sample-and-hold b. the adc pins should not be driven before the v dda1 , v dda2 , and adcinb3 c1 5 5 i pins should not be driven before the v dda1 , v dda2 , and v ddaio pins have been fully powered up. adcinb2 b1 4 4 i v ddaio pins have been fully powered up. adcinb1 c3 3 3 i adcinb0 c2 2 2 i adcrefp e2 11 11 i/o adc voltage reference output (2 v). requires a low esr (50 m ? ? 1.5 ? ) ceramic bypass capacitor of 10 f to analog ground. (can accept external reference input (2 v) if the software bit is enabled for this mode. 1?10 f low esr capacitor can be used in the external reference mode.) adcrefm e4 10 10 i/o adc voltage reference output (1 v). requires a low esr (50 m ? ? 1.5 ? ) ceramic bypass capacitor of 10 f to analog ground. (can accept external reference input (1 v) if the software bit is enabled for this mode. 1?10 f low esr capacitor can be used in the external reference mode.) adcresext f2 16 16 o adc external current bias resistor (24.9 k ? 5% ) adcbgrefin e6 164 116 i test pin. reserved for ti. must be left unconnected. avssrefbg e3 12 12 i adc analog gnd avddrefbg e1 13 13 i adc analog power (3.3-v) adclo b3 175 127 i common low side analog input. connect to analog ground. v ssa1 f3 15 15 i adc analog gnd v ssa2 c5 165 117 i adc analog gnd v dda1 f4 14 14 i adc analog 3.3-v supply v dda2 a5 166 118 i adc analog 3.3-v supply v ss1 c6 163 115 i adc digital gnd v dd1 a6 162 114 i adc digital 1.8-v (or 1.9-v) supply v ddaio b2 1 1 3.3-v analog i/o power pin v ssaio a2 176 128 analog i/o ground pin ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 24 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) name description pu/pd i/o/z ? pin no. name description pu/pd i/o/z ? 128-pin pbk 176-pin pgf 179-pin ghh power signals v dd h1 23 20 v dd l1 37 29 v dd p5 56 42 v dd p9 75 56 1.8-v or 1.9-v core digital power pins. see section 6.2, v dd p12 ? 63 1.8-v or 1.9-v core digital power pins. see section 6.2 , recommended operating conditions, for voltage v dd k12 100 74 recommended operating conditions, for voltage requirements. v dd g12 112 82 requirements. v dd c14 128 94 v dd b10 143 102 v dd c8 154 110 v ss g4 19 17 v ss k1 32 26 v ss l2 38 30 v ss p4 52 39 v ss k6 58 ? v ss p8 70 53 v ss m10 78 59 v ss l11 86 62 core and digital i/o ground pins v ss k13 99 73 core and digital i/o ground pins v ss j14 105 ? v ss g13 113 ? v ss e14 120 88 v ss b14 129 95 v ss d10 142 ? v ss c10 ? 103 v ss b8 153 109 v ddio j4 31 25 v ddio l7 64 49 v ddio l10 81 ? 3.3-v i/o digital power pins v ddio n14 ? ? 3.3-v i/o digital power pins v ddio g11 114 83 v ddio e9 145 104 v dd3vfl n8 69 52 3.3-v flash core power pin. this pin should be connected to 3.3 v at all times after power-up sequence requirements have been met. this pin is used as vddio in rom parts and must be connected to 3.3 v in rom parts as well. ? typical drive strength of the output buffer for all pins is 4 ma except for tdo, xclkout, xf, xintf, emu0, and emu1 pins, which are 8 ma. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 25 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) pin no. ? gpio peripheral signal 179-pin ghh 176-pin pgf 128-pin pbk i/o/z ? pu/pd description gpio or peripheral signals gpioa or eva signals gpioa0 pwm1 (o) m12 92 68 i/o/z pu gpio or pwm output pin #1 gpioa1 pwm2 (o) m14 93 69 i/o/z pu gpio or pwm output pin #2 gpioa2 pwm3 (o) l12 94 70 i/o/z pu gpio or pwm output pin #3 gpioa3 pwm4 (o) l13 95 71 i/o/z pu gpio or pwm output pin #4 gpioa4 pwm5 (o) k11 98 72 i/o/z pu gpio or pwm output pin #5 gpioa5 pwm6 (o) k14 101 75 i/o/z pu gpio or pwm output pin #6 gpioa6 t1pwm_t1cmp (i) j11 102 76 i/o/z pu gpio or timer 1 output gpioa7 t2pwm_t2cmp (i) j13 104 77 i/o/z pu gpio or timer 2 output gpioa8 cap1_qep1 (i) h10 106 78 i/o/z pu gpio or capture input #1 gpioa9 cap2_qep2 (i) h11 107 79 i/o/z pu gpio or capture input #2 gpioa10 cap3_qepi1 (i) h12 109 80 i/o/z pu gpio or capture input #3 gpioa11 tdira (i) f14 116 85 i/o/z pu gpio or timer direction gpioa12 tclkina (i) f13 117 86 i/o/z pu gpio or timer clock input gpioa13 c1trip (i) e13 122 89 i/o/z pu gpio or compare 1 output trip gpioa14 c2trip (i) e11 123 90 i/o/z pu gpio or compare 2 output trip gpioa15 c3trip (i) f10 124 91 i/o/z pu gpio or compare 3 output trip gpiob or evb signals gpiob0 pwm7 (o) n2 45 33 i/o/z pu gpio or pwm output pin #7 gpiob1 pwm8 (o) p2 46 34 i/o/z pu gpio or pwm output pin #8 gpiob2 pwm9 (o) n3 47 35 i/o/z pu gpio or pwm output pin #9 gpiob3 pwm10 (o) p3 48 36 i/o/z pu gpio or pwm output pin #10 gpiob4 pwm11 (o) l4 49 37 i/o/z pu gpio or pwm output pin #11 gpiob5 pwm12 (o) m4 50 38 i/o/z pu gpio or pwm output pin #12 gpiob6 t3pwm_t3cmp (i) k5 53 40 i/o/z pu gpio or timer 3 output gpiob7 t4pwm_t4cmp (i) n5 55 41 i/o/z pu gpio or timer 4 output gpiob8 cap4_qep3 (i) m5 57 43 i/o/z pu gpio or capture input #4 gpiob9 cap5_qep4 (i) m6 59 44 i/o/z pu gpio or capture input #5 gpiob10 cap6_qepi2 (i) p6 60 45 i/o/z pu gpio or capture input #6 gpiob11 tdirb (i) l8 71 54 i/o/z pu gpio or timer direction gpiob12 tclkinb (i) k8 72 55 i/o/z pu gpio or timer clock input gpiob13 c4trip (i) n6 61 46 i/o/z pu gpio or compare 4 output trip gpiob14 c5trip (i) l6 62 47 i/o/z pu gpio or compare 5 output trip gpiob15 c6trip (i) k7 63 48 i/o/z pu gpio or compare 6 output trip ? typical drive strength of the output buffer for all pins [except tdo, xclkout, xf, xintf, emu0, and emu1 pins] is 4 ma typical. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 26 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) pin no. ? gpio peripheral signal 179-pin ghh 176-pin pgf 128-pin pbk i/o/z ? pu/pd description gpiod or eva signals gpiod0 t1ctrip_pdpinta (i) h14 110 81 i/o/z pu timer 1 compare output trip gpiod1 t2ctrip /evasoc (i) g10 115 84 i/o/z pu timer 2 compare output trip or external adc start-of-conversion ev-a gpiod or evb signals gpiod5 t3ctrip_pdpintb (i) p10 79 60 i/o/z pu timer 3 compare output trip gpiod6 t4ctrip /evbsoc (i) p11 83 61 i/o/z pu timer 4 compare output trip or external adc start-of-conversion ev-b gpioe or interrupt signals gpioe0 xint1_xbio (i) d9 149 106 i/o/z ? gpio or xint1 or xbio input gpioe1 xint2_adcsoc (i) d8 151 108 i/o/z ? gpio or xint2 or adc start of conversion gpioe2 xnmi_xint13 (i) e8 150 107 i/o/z pu gpio or xnmi or xint13 gpiof or spi signals gpiof0 spisimoa (o) m1 40 31 i/o/z ? gpio or spi slave in, master out gpiof1 spisomia (i) n1 41 32 i/o/z ? gpio or spi slave out, master in gpiof2 spiclka (i/o) k2 34 27 i/o/z ? gpio or spi clock gpiof3 spistea (i/o) k4 35 28 i/o/z ? gpio or spi slave transmit enable gpiof or sci-a signals gpiof4 scitxda (o) c7 155 111 i/o/z pu gpio or sci asynchronous serial port tx data gpiof5 scirxda (i) a7 157 112 i/o/z pu gpio or sci asynchronous serial port rx data gpiof or can signals gpiof6 cantxa (o) n12 87 64 i/o/z pu gpio or ecan transmit data gpiof7 canrxa (i) n13 89 65 i/o/z pu gpio or ecan receive data gpiof or mcbsp signals gpiof8 mclkxa (i/o) j1 28 23 i/o/z pu gpio or transmit clock gpiof9 mclkra (i/o) h2 25 21 i/o/z pu gpio or receive clock gpiof10 mfsxa (i/o) h4 26 22 i/o/z pu gpio or transmit frame synch gpiof11 mfsra (i/o) j2 29 24 i/o/z pu gpio or receive frame synch gpiof12 mdxa (o) g1 22 19 i/o/z ? gpio or transmitted serial data gpiof13 mdra (i) g2 20 18 i/o/z pu gpio or received serial data ? typical drive strength of the output buffer for all pins [except tdo, xclkout, xf, xintf, emu0, and emu1 pins] is 4 ma typical. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. introduction 27 april 2001 ? revised december 2004 sprs174l table 2?2. signal descriptions ? (continued) pin no. ? gpio peripheral signal 179-pin ghh 176-pin pgf 128-pin pbk i/o/z ? pu/pd description gpiof or xf cpu output signal gpiof14 xf_xplldis (o) a11 140 101 i/o/z pu this pin has three functions: 1. xf ? general-purpose output pin. 2. xplldis ? this pin will be sampled during reset to check if the pll needs to be disabled. the pll will be disabled if this pin is sensed low. halt and standby modes cannot be used when the pll is disabled. 3. gpio ? gpio function gpiog or sci-b signals gpiog4 scitxdb (o) p14 90 66 i/o/z ? gpio or sci asynchronous serial port transmit data gpiog5 scirxdb (i) m13 91 67 i/o/z ? gpio or sci asynchronous serial port receive data ? typical drive strength of the output buffer for all pins [except tdo, xclkout, xf, xintf, emu0, and emu1 pins] is 4 ma typical. ? i = input, o = output, z = high impedance pu = pin has internal pullup; pd = pin has internal pulldown. pullup/pulldown strength is given in section 6.3. note: other than the power supply pins, no pin should be driven before the 3.3-v rail has reached recommended operating conditions. however, it is acceptable for an i/o pin to ramp along with the 3.3-v supply. functional overview 28 april 2001 ? revised december 2004 sprs174l 3 functional overview 16 int14 nmi int13 memory bus m1 saram 1k x 16 flash 128k x 16 (f2812) 128k x 16 (f2811) 64k x 16 (f2810) boot rom 4k 16 ecan scia/scib 12-bit adc external interrupt control (xint1/2/13, xnmi) eva/evb memory bus otp 1k x 16 mcbsp system control (oscillator and pll + peripheral clocking + low-power modes + watchdog) fifo fifo pie (96 interrupts) ? rs spi fifo tint0 tint1 tint2 control address(19) data(16) external interface (xintf) ? 16 channels ? 45 of the possible 96 interrupts are used on the devices. ? xintf is available on the f2812 and c2812 devices only. on c281x devices, the otp is replaced with a 1k x 16 block of rom gpio pins xrs x1/xclkin x2 xf_xplldis protected by the code-security module. xint13 g p i o m u x l1 saram 4k x 16 xnmi l0 saram 4k x 16 functional overview 29 april 2001 ? revised december 2004 sprs174l 3.1 memory map 32) (enabled if vmap = 0) data space prog space m0 saram (1k 16) m1 saram (1k 16) 16) 0x00 0040 0x00 0400 0x00 0800 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 16, secure block) peripheral frame 1 (4k 16, protected) 16, protected) l1 saram (4k 16, secure block) reserved otp (or rom) (1k 16, secure block) flash (or rom) (128k 16, secure block) 128-bit password h0 saram (8k 16) reserved boot rom (4k 16) (enabled if mp/mc = 0) brom vector - rom (32 32) (enabled if vmap = 1, mp/mc = 0, enpie = 0) 0x00 0d00 0x00 0e00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 a000 0x3d 7800 0x3d 7c00 0x3f 7ff8 0x3f 8000 0x3f a000 0x3f f000 0x3f ffc0 high 64k (24x/240x equivalent program space) data space prog space reserved xintf zone 0 (8k 16, xzcs0and1 ) xintf zone 1 (8k 16, xzcs0and1 ) (protected) 16, xzcs2 ) xintf zone 6 (0.5m 16, xzcs6and7 ) reserved xintf zone 7 (16k 16, xzcs6and7 ) (enabled if mp/mc = 1) xintf vector - ram (32 32) (enabled if vmap = 1, mp/mc = 1, enpie = 0) on-chip memory external memory xintf only one of these vector maps?m0 vector, pie vector, brom vector, xintf vector?should be enabled at a time. legend: 0x08 0000 0x00 4000 0x10 0000 0x18 0000 0x3f c000 0x00 2000 notes: a. memory blocks are not to scale. b. reserved locations are reserved for future expansion. application should not access these areas. c. boot rom and zone 7 memory maps are active either in on-chip or xintf zone depending on mp/mc , not in both. d. peripheral frame 0, peripheral frame 1, and peripheral frame 2 memory maps are restricted to data memory only. user program cannot access these memory maps in program space. e. ?protected? means the order of write followed by read operations is preserved rather than the pipeline order. f. certain memory ranges are eallow protected against spurious writes after configuration. g. zones 0 and 1 and zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations. figure 3?2. f2812/c2812 memory map (see notes a through e) functional overview 30 april 2001 ? revised december 2004 sprs174l block start address low 64k (24x/240x equivalent data space) 0x00 0000 m0 vector ? ram (32 32) (enabled if vmap = 0) data space prog space m0 saram (1k 16) m1 saram (1k 16) 16) 0x00 0040 0x00 0400 0x00 0800 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 16, secure block) peripheral frame 1 (4k 16, protected) 16, protected) l1 saram (4k 16, secure block) reserved otp (or rom) (1k 16, secure block) flash (or rom) (128k 16, secure block) 128-bit password h0 saram (8k 16) reserved boot rom (4k 16) (enabled if mp/mc = 0) brom vector - rom (32 32) (enabled if vmap = 1, mp/mc = 0, enpie = 0) 0x00 0d00 0x00 0e00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 a000 0x3d 7800 0x3d 7c00 0x3f 7ff8 0x3f 8000 0x3f a000 0x3f f000 0x3f ffc0 high 64k (24x/240x equivalent program space) on-chip memory only one of these vector maps?m0 vector, pie vector, brom vector, xintf vector?should be enabled at a time. legend: notes: a. memory blocks are not to scale. b. reserved locations are reserved for future expansion. application should not access these areas. c. peripheral frame 0, peripheral frame 1, and peripheral frame 2 memory maps are restricted to data memory only. user program cannot access these memory maps in program space. d. ?protected? means the order of write followed by read operations is preserved rather than the pipeline order. e. certain memory ranges are eallow protected against spurious writes after configuration. figure 3?3. f2811/c2811 memory map (see notes a through e) functional overview 31 april 2001 ? revised december 2004 sprs174l block start address low 64k (24x/240x equivalent data space) 0x00 0000 m0 vector ? ram (32 32) (enabled if vmap = 0) data space prog space m0 saram (1k 16) m1 saram (1k 16) 16) 0x00 0040 0x00 0400 0x00 0800 pie vector - ram (256 16) (enabled if vmap = 1, enpie = 1) 16, secure block) peripheral frame 1 (4k 16, protected) 16, protected) l1 saram (4k 16, secure block) reserved reserved flash (or rom) (64k 16, secure block) 128-bit password h0 saram (8k 16) reserved boot rom (4k 16) (enabled if mp/mc = 0) brom vector - rom (32 32) (enabled if vmap = 1, mp/mc = 0, enpie = 0) 0x00 0d00 0x00 0e00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 a000 0x3d 7c00 0x3e 8000 0x3f 7ff8 0x3f 8000 0x3f a000 0x3f f000 0x3f ffc0 high 64k (24x/240x equivalent program space) on-chip memory only one of these vector maps?m0 vector, pie vector, brom vector?should be enabled at a time. legend: otp (or rom) (1k 16, secure block) 0x3d 7800 notes: a. memory blocks are not to scale. b. reserved locations are reserved for future expansion. application should not access these areas. c. peripheral frame 0, peripheral frame 1, and peripheral frame 2 memory maps are restricted to data memory only. user program cannot access these memory maps in program space. d. ?protected? means the order of write followed by read operations is preserved rather than the pipeline order. e. certain memory ranges are eallow protected against spurious writes after configuration. figure 3?4. f2810/c2810 memory map (see notes a through e) functional overview 32 april 2001 ? revised december 2004 sprs174l table 3?1. addresses of flash sectors in f2812 and f2811 address range program and data space 0x3d 8000 0x3d 9fff sector j, 8k x 16 0x3d a000 0x3d bfff sector i, 8k x 16 0x3d c000 0x3d ffff sector h, 16k x 16 0x3e 0000 0x3e 3fff sector g, 16k x 16 0x3e 4000 0x3e 7fff sector f, 16k x 16 0x3e 8000 0x3e bfff sector e, 16k x 16 0x3e c000 0x3e ffff sector d, 16k x 16 0x3f 0000 0x3f 3fff sector c, 16k x 16 0x3f 4000 0x3f 5fff sector b, 8k x 16 0x3f 6000 sector a, 8k x 16 0x3f 7f80 0x3f 7ff5 program to 0x0000 when using the code security module 0x3f 7ff6 0x3f 7ff7 boot-to-flash (or rom) entry point (program branch instruction here) 0x3f 7ff8 0x3f 7fff security password (128-bit) (do not program to all zeros) table 3?2. addresses of flash sectors in f2810 address range program and data space 0x3e 8000 0x3e bfff sector e, 16k x 16 0x3e c000 0x3e ffff sector d, 16k x 16 0x3f 0000 0x3f 3fff sector c, 16k x 16 0x3f 4000 0x3f 5fff sector b, 8k x 16 0x3f 6000 sector a, 8k x 16 0x3f 7f80 0x3f 7ff5 program to 0x0000 when using the code security module 0x3f 7ff6 0x3f 7ff7 boot-to-flash (or rom) entry point (program branch instruction here) 0x3f 7ff8 0x3f 7fff security password (128-bit) (do not program to all zeros) functional overview 33 april 2001 ? revised december 2004 sprs174l the ?low 64k? of the memory address range maps into the data space of the 240x. the ?high 64k? of the memory address range maps into the program space of the 24x/240x. 24x/240x-compatible code will only execute from the ?high 64k? memory area. hence, the top 32k of flash/rom and h0 saram block can be used to run 24x/240x-compatible code (if mp/mc mode is low) or, on the 2812, code can be executed from xintf zone 7 (if mp/mc mode is high). the xintf consists of five independent zones. one zone has its own chip select and the remaining four zones share two chip selects. each zone can be programmed with its own timing (wait states) and to either sample or ignore external ready signal. this makes interfacing to external peripherals easy and glueless. note: the chip selects of xintf zone 0 and zone 1 are merged together into a single chip select (xzcs0and1 ); and the chip selects of xintf zone 6 and zone 7 are merged together into a single chip select (xzcs6and7 ). see section 3.5, ?external interface, xintf (2812 only)?, for details. peripheral frame 1, peripheral frame 2, and xintf zone 1 are grouped together so as to enable these blocks to be ?write/read peripheral block protected?. the ?protected? mode ensures that all accesses to these blocks happen as written. because of the c28x pipeline, a write immediately followed by a read, to different memory locations, will appear in reverse order on the memory bus of the cpu. this can cause problems in certain peripheral applications where the user expected the write to occur first (as written). the c28x cpu supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written (the penalty is extra cycles are added to align the operations). this mode is programmable and by default, it will protect the selected zones. on the 2812, at reset, xintf zone 7 is accessed if the xmp/mc pin is pulled high. this signal selects microprocessor or microcomputer mode of operation. in microprocessor mode, zone 7 is mapped to high memory such that the vector table is fetched externally. the boot rom is disabled in this mode. in microcomputer mode, zone 7 is disabled such that the vectors are fetched from boot rom. this allows the user to either boot from on-chip memory or from off-chip memory. the state of the xmp/mc signal on reset is stored in an mp/mc mode bit in the xintcnf2 register. the user can change this mode in software and hence control the mapping of boot rom and xintf zone 7. no other memory blocks are affected by xmp/mc . i/o space is not supported on the 2812 xintf. the wait states for the various spaces in the memory map area are listed in table 3?3. functional overview 34 april 2001 ? revised december 2004 sprs174l table 3?3. wait states area wait-states comments m0 and m1 sarams 0-wait fixed peripheral frame 0 0-wait fixed peripheral frame 1 0-wait (writes) 2-wait (reads) fixed peripheral frame 2 0-wait (writes) 2-wait (reads) fixed l0 & l1 sarams 0-wait fixed otp (or rom) programmable, 1-wait minimum programmed via the flash registers. 1-wait-state operation is possible at a reduced cpu frequency. see section 3.2.6, flash (f281x only), for more information. flash (or rom) programmable, 0-wait minimum programmed via the flash registers. 0-wait-state operation is possible at reduced cpu frequency. the csm password locations are hardwired for 16 wait-states. see section 3.2.6, flash (f281x only), for more information. h0 saram 0-wait fixed boot-rom 1-wait fixed xintf programmable, 1-wait minimum programmed via the xintf registers. cycles can be extended by external memory or peripheral. 0-wait operation is not possible. 3.2 brief descriptions 3.2.1 c28x cpu the c28x ? dsp generation is the newest member of the tms320c2000 ? dsp platform. the c28x is source code compatible to the 24x/240x dsp devices, hence existing 240x users can leverage their significant software investment. additionally, the c28x is a very efficient c/c++ engine, hence enabling users to develop not only their system control software in a high-level language, but also enables math algorithms to be developed using c/c++. the c28x is as efficient in dsp math tasks as it is in system control tasks that typically are handled by microcontroller devices. this efficiency removes the need for a second processor in many systems. the 32 x 32-bit mac capabilities of the c28x and its 64-bit processing capabilities, enable the c28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. the c28x has an 8-level-deep protected pipeline with pipelined memory accesses. this pipelining enables the c28x to execute at high speeds without resorting to expensive high-speed memories. special branch-look-ahead hardware minimizes the latency for conditional discontinuities. special store conditional operations further improve performance. c28x and tms320c2000 are trademarks of texas instruments. functional overview 35 april 2001 ? revised december 2004 sprs174l 3.2.2 memory bus (harvard bus architecture) as with many dsp type devices, multiple busses are used to move data between the memories and peripherals and the cpu. the c28x memory bus architecture contains a program read bus, data read bus and data write bus. the program read bus consists of 22 address lines and 32 data lines. the data read and write busses consist of 32 address lines and 32 data lines each. the 32-bit-wide data busses enable single cycle 32-bit operations. the multiple bus architecture, commonly termed ?harvard bus?, enables the c28x to fetch an instruction, read a data value and write a data value in a single cycle. all peripherals and memories attached to the memory bus will prioritize memory accesses. generally, the priority of memory bus accesses can be summarized as follows: highest: data writes ? program writes ? data reads program reads ? lowest: fetches ? 3.2.3 peripheral bus to enable migration of peripherals between various texas instruments (ti) dsp family of devices, the f281x and c281x adopt a peripheral bus standard for peripheral interconnect. the peripheral bus bridge multiplexes the various busses that make up the processor ?memory bus? into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. two versions of the peripheral bus are supported on the f281x and c281x. one version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with c240x-compatible peripherals. the other version supports both 16- and 32-bit accesses (called peripheral frame 1). 3.2.4 real-time jtag and analysis the f281x and c281x implement the standard ieee 1149.1 jtag interface. additionally, the f281x and c281x support real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts. the user can also single step through non-time critical code while enabling time-critical interrupts to be serviced without interference. the f281x and c281x implement the real-time mode in hardware within the cpu. this is a unique feature to the f281x and c281x, no software monitor is required. additionally, special analysis hardware is provided which allows the user to set hardware breakpoint or data/address watch-points and generate various user selectable break events when a match occurs. 3.2.5 external interface (xintf) (2812 only) this asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. the chip-select lines are mapped to five external zones, zones 0, 1, 2, 6, and 7. zones 0 and 1 share a single chip-select; zones 6 and 7 also share a single chip-select. each of the five zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. the programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals. ? simultaneous data and program writes cannot occur on the memory bus. ? simultaneous program reads and fetches cannot occur on the memory bus. functional overview 36 april 2001 ? revised december 2004 sprs174l 3.2.6 flash (f281x only) the f2812 and f2811 contain 128k x 16 of embedded flash memory, segregated into four 8k x 16 sectors, and six 16k x 16 sectors. the f2810 has 64k x 16 of embedded flash, segregated into two 8k x 16 sectors, and three 16k x 16 sectors. all three devices also contain a single 1k x 16 of otp memory at address range 0x3d 7800 ? 0x3d 7bff. the user can individually erase, program, and validate a flash sector while leaving other sectors untouched. however, it is not possible to use one sector of the flash or the otp to execute flash algorithms that erase/program other sectors. special memory pipelining is provided to enable the flash module to achieve higher performance. the flash/otp is mapped to both program and data space; therefore, it can be used to execute code or store data information. note: the f2810/f281 1/f2812 flash and otp wait states can be configured by the application. this allows applications running at slower frequencies to configure the flash to use fewer wait states. flash ef fective performance can be improved by enabling the flash pipeline mode in the flash options register. with this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait state configuration alone. the exact performance gain when using the flash pipeline mode is application-dependent. the pipeline mode is not available for the otp block. for more information on the flash options, flash wait-state, and otp wait-state registers, see the tms320x281x system control and interrupts reference guide (literature number spru078). 3.2.7 rom (c281x only) the c2812 and c2811 contain 128k x 16 of rom. the c2810 has 64k x 16 of rom. in addition to this, there is a 1k x 16 rom block that replaces the otp memory available in flash devices. for information on how to submit rom codes to ti, see the tms320c28x cpu and instruction set reference guide (literature number spru430). 3.2.8 m0, m1 sarams all c28x devices contain these two blocks of single access memory, each 1k x 16 in size. the stack pointer points to the beginning of block m1 on reset. the m0 block overlaps the 240x device b0, b1, b2 ram blocks and hence the mapping of data variables on the 240x devices can remain at the same physical address on c28x devices. the m0 and m1 blocks, like all other memory blocks on c28x devices, are mapped to both program and data space. hence, the user can use m0 and m1 to execute code or for data variables. the partitioning is performed within the linker. the c28x device presents a unified memory map to the programmer. this makes for easier programming in high-level languages. 3.2.9 l0, l1, h0 sarams the f281x and c281x contain an additional 16k x 16 of single-access ram, divided into 3 blocks (4k + 4k + 8k). each block can be independently accessed hence minimizing pipeline stalls. each block is mapped to both program and data space. 3.2.10 boot rom the boot rom is factory-programmed with boot-loading software. the boot rom program executes after device reset and checks several gpio pins to determine which boot mode to enter. for example, the user can select to execute code already present in the internal flash or download new software to internal ram through one of several serial ports. other boot modes exist as well. the boot rom also contains standard tables, such as sin/cos waveforms, for use in math-related algorithms. table 3?4 shows the details of how various boot modes may be invoked. see the tms320x281x dsp boot rom reference guide (literature number spru095), for more information. functional overview 37 april 2001 ? revised december 2004 sprs174l table 3?4. boot mode selection gpiof4 gpiof12 gpiof3 gpiof2 (scitxda) (mdxa) (spistea) (spiclk) mode selected ? pu no pu no pu no pu jump to flash/rom address 0x3f 7ff6 a branch instruction must have been programmed here prior to reset to re?direct code excution as desired. 1 x x x call spi_boot to load from an external serial spi eeprom 0 1 x x call sci_boot to load from sci-a 0 0 1 1 jump to h0 saram address 0x3f 8000 0 0 1 0 jump to otp address 0x3d 7800 0 0 0 1 call parallel_boot to load from gpio port b 0 0 0 0 ? pu = pin has an internal pullup no pu = pin does not have an internal pullup ? extra care must be taken due to any affect toggling spiclk to select a boot mode may have on external logic. if the boot mode selected is flash, h0, or otp, then no external code is loaded by the bootloader. 3.2.11 security the f281x and c281x support high levels of security to protect the user firmware from being reverse-engineered. the security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the flash. one code security module (csm) is used to protect the flash/rom/otp and the l0/l1 saram blocks. the security feature prevents unauthorized users from examining the memory contents via the jtag port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. to enable access to the secure blocks, the user must write the correct 128-bit ?key? value, which matches the value stored in the password locations within the flash/rom. note: for code security operation, all addresses between 0x3f7f80 and 0x3f7ff5 cannot be used as program code or data, but must be programmed to 0x0000 when the code security passwords are programmed. if security is not a concern, then these addresses may be used for code or data. the 128-bit password (at 0x3f 7ff8 ? 0x3f 7fff) must not be programmed to zeros. doing so would permanently lock the device. code security module disclaimer the code security module (?csm?) included on this device was designed to password protect the data stored in the associated memory (either rom or flash) and is warranted by texas instruments (ti), in accordance with its standard terms and conditions, to conform to ti?s published specifications for the warranty period applicable for this device. ti does not, however, warrant or represent tha t the csm cannot be compromised or breached or that the data stored in the associated memory cannot be accessed through other means. moreover, except as set forth above, ti makes no warranties or representations concerning the csm or operation of this device, including any implied w arranties of merchantability or fitness for a particular purpose. functional overview 38 april 2001 ? revised december 2004 sprs174l in no event shall ti be liable for any consequential, special, indirect, incidental, or punitive damages, however caused, arising in any way out of your use of the csm or this device, whether or not ti has been advised of the possibility of such damages. excluded damages include, but are not limited to loss of data, loss of goodwill, loss of use or interruption of business or other economic loss. 3.2.12 peripheral interrupt expansion (pie) block the pie block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. the pie block can support up to 96 peripheral interrupts. on the f281x and c281x, 45 of the possible 96 interrupts are used by peripherals. the 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 cpu interrupt lines (int1 to int12). each of the 96 interrupts is, supported by its own vector stored in a dedicated ram block that can be overwritten by the user. the vector is, automatically fetched by the cpu on servicing the interrupt. it takes 8 cpu clock cycles to fetch the vector and save critical cpu registers. hence the cpu can quickly respond to interrupt events. prioritization of interrupts is controlled in hardware and software. each individual interrupt can be enabled/disabled within the pie block. 3.2.13 external interrupts (xint1, xint2, xint13, xnmi) the f281x and c281x support three masked external interrupts (xint1, 2, 13). xint13 is combined with one non-masked external interrupt (xnmi). the combined signal name is xnmi_xint13. each of the interrupts can be selected for negative or positive edge triggering and can also be enabled/disabled (including the xnmi). the masked interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. this counter can be used to accurately time stamp the interrupt. 3.2.14 oscillator and pll the f281x and c281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. a pll is provided supporting up to 10-input clock-scaling ratios. the pll ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. refer to the electrical specification section for timing details. the pll block can be set in bypass mode. 3.2.15 watchdog the f281x and c281x support a watchdog timer. the user software must regularly reset the watchdog counter within a certain time frame; otherwise, the watchdog will generate a reset to the processor. the watchdog can be disabled if necessary. 3.2.16 peripheral clocking the clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use. additionally, the system clock to the serial ports (except ecan) and the event managers, cap and qep blocks can be scaled relative to the cpu clock. this enables the timing of peripherals to be decoupled from increasing cpu clock speeds. functional overview 39 april 2001 ? revised december 2004 sprs174l 3.2.17 low-power modes the f281x and c281x devices are full static cmos devices. three low-power modes are provided: idle: place cpu into low-power mode. peripheral clocks may be turned off selectively and only those peripherals that need to function during idle are left operating. an enabled interrupt from an active peripheral will wake the processor from idle mode. standby: turn off clock to cpu and peripherals. this mode leaves the oscillator and pll functional. an external interrupt event will wake the processor and the peripherals. execution begins on the next valid cycle after detection of the interrupt event. halt: turn off oscillator. this mode basically shuts down the device and places it in the lowest possible power consumption mode. only a reset or xnmi will wake the device from this mode. 3.2.18 peripheral frames 0, 1, 2 (pfn) the f281x and c281x segregate peripherals into three sections. the mapping of peripherals is as follows: pf0: xintf: external interface configuration registers (2812 only) pie: pie interrupt enable and control registers plus pie vector table flash: flash control, programming, erase, verify registers timers: cpu-timers 0, 1, 2 registers csm: code security module key registers pf1: ecan: ecan mailbox and control registers pf2: sys: system control registers gpio: gpio mux configuration and control registers ev: event manager (eva/evb) control registers mcbsp: mcbsp control and tx/rx registers sci: serial communications interface (sci) control and rx/tx registers spi: serial peripheral interface (spi) control and rx/tx registers adc: 12-bit adc registers 3.2.19 general-purpose input/output (gpio) multiplexer most of the peripheral signals are multiplexed with general-purpose i/o (gpio) signals. this enables the user to use a pin as gpio if the peripheral signal or function is not used. on reset, all gpio pins are configured as inputs. the user can then individually program each pin for gpio mode or peripheral signal mode. for specific inputs, the user can also select the number of input qualification cycles. this is to filter unwanted noise glitches. 3.2.20 32-bit cpu-timers (0, 1, 2) cpu-timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. the timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. the counter is decremented at the cpu clock speed divided by the prescale value setting. when the counter reaches zero, it is automatically reloaded with a 32-bit period value. cpu-timer 2 is reserved for real-time os (rtos)/bios applications. cpu-timer 1 is also reserved for ti system functions. cpu-timer 2 is connected to int14 of the cpu. cpu-timer 1 can be connected to int13 of the cpu. cpu-timer 0 is for general use and is connected to the pie block. functional overview 40 april 2001 ? revised december 2004 sprs174l 3.2.21 control peripherals the f281x and c281x support the following peripherals which are used for embedded control and communication: ev: the event manager module includes general-purpose timers, full-compare/pwm units, capture inputs (cap) and quadrature-encoder pulse (qep) circuits. two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. the event managers on the f281x and c281x are compatible to the event managers on the 240x devices (with some minor enhancements). adc: the adc block is a 12-bit converter, single ended, 16-channels. it contains two sample-and-hold units for simultaneous sampling. 3.2.22 serial port peripherals the f281x and c281x support the following serial communication peripherals: ecan: this is the enhanced version of the can peripheral. it supports 32 mailboxes, time stamping of messages, and is can 2.0b-compliant. mcbsp: this is the multichannel buffered serial port that is used to connect to e1/t1 lines, phone-quality codecs for modem applications or high-quality stereo-quality audio dac devices. the mcbsp receive and transmit registers are supported by a 16-level fifo. this significantly reduces the overhead for servicing this peripheral. spi: the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multi-device communications are supported by the master/slave operation of the spi. on the f281x and c281x, the port supports a 16-level, receive and transmit fifo for reducing servicing overhead. sci: the serial communications interface is a two-wire asynchronous serial port, commonly known as uart. on the f281x and c281x, the port supports a 16-level, receive and transmit fifo for reducing servicing overhead. 3.3 register map the f281x and c281x devices contain three peripheral register spaces. the spaces are categorized as follows: ? peripheral frame 0: these are peripherals that are mapped directly to the cpu memory bus. see table 3?5. ? peripheral frame 1: these are peripherals that are mapped to the 32-bit peripheral bus. see table 3?6. ? peripheral frame 2: these are peripherals that are mapped to the 16-bit peripheral bus. see table 3?7. functional overview 41 april 2001 ? revised december 2004 sprs174l table 3?5. peripheral frame 0 registers ? name address range size (x16) access type ? device emulation registers 0x00 0880 0x00 09ff 384 eallow protected reserved 0x00 0a00 0x00 0a7f 128 flash registers 0x00 0a80 0x00 0adf 96 eallow protected csm protected code security module registers 0x00 0ae0 0x00 0aef 16 eallow protected reserved 0x00 0af0 0x00 0b1f 48 xintf registers 0x00 0b20 0x00 0b3f 32 not eallow protected reserved 0x00 0b40 0x00 0bff 192 cpu-timer0/1/2 registers 0x00 0c00 0x00 0c3f 64 not eallow protected reserved 0x00 0c40 0x00 0cdf 160 pie registers 0x00 0ce0 0x00 0cff 32 not eallow protected pie vector table 0x00 0d00 0x00 0dff 256 eallow protected reserved 0x00 0e00 0x00 0fff 512 ? registers in frame 0 support 16-bit and 32-bit accesses. ? if registers are eallow protected, then writes cannot be performed until the user executes the eallow instruction. the edis ins truction disables writes. this prevents stray code or pointers from corrupting register contents. the flash registers are also protected by the code security module (csm). table 3?6. peripheral frame 1 registers ? name address range size (x16) access type ecan registers 0x00 6000 0x00 60ff 256 (128 x 32) some ecan control registers (and selected bits in other ecan control registers) are eallow-protected. ecan mailbox ram 0x00 6100 0x00 61ff 256 (128 x 32) not eallow-protected reserved 0x00 6200 0x00 6fff 3584 ? the ecan control registers only support 32-bit read/write operations. all 32-bit accesses are aligned to even address boundarie s. functional overview 42 april 2001 ? revised december 2004 sprs174l table 3?7. peripheral frame 2 registers ? name address range size (x16) access type reserved 0x00 7000 0x00 700f 16 system control registers 0x00 7010 0x00 702f 32 eallow protected reserved 0x00 7030 0x00 703f 16 spi-a registers 0x00 7040 0x00 704f 16 not eallow protected sci-a registers 0x00 7050 0x00 705f 16 not eallow protected reserved 0x00 7060 0x00 706f 16 external interrupt registers 0x00 7070 0x00 707f 16 not eallow protected reserved 0x00 7080 0x00 70bf 64 gpio mux registers 0x00 70c0 0x00 70df 32 eallow protected gpio data registers 0x00 70e0 0x00 70ff 32 not eallow protected adc registers 0x00 7100 0x00 711f 32 not eallow protected reserved 0x00 7120 0x00 73ff 736 ev-a registers 0x00 7400 0x00 743f 64 not eallow protected reserved 0x00 7440 0x00 74ff 192 ev-b registers 0x00 7500 0x00 753f 64 not eallow protected reserved 0x00 7540 0x00 774f 528 sci-b registers 0x00 7750 0x00 775f 16 not eallow protected reserved 0x00 7760 0x00 77ff 160 mcbsp registers 0x00 7800 0x00 783f 64 not eallow protected reserved 0x00 7840 0x00 7fff 1984 ? peripheral frame 2 only allows 16-bit accesses. all 32-bit accesses are ignored (invalid data may be returned or written). functional overview 43 april 2001 ? revised december 2004 sprs174l 3.4 device emulation registers these r egisters are used to control the protection mode of the c28x cpu and to monitor some critical device signals. the registers are defined in table 3?8. table 3?8. device emulation registers name address range size (x16) description devicecnf 0x00 0880 0x00 0881 2 device configuration register reserved 0x00 0882 1 not supported on revision c and later silicon deviceid 0x00 0883 1 device id register (0x0003 ? silicon ? rev. c and d) device id register (0x0004 ? reserved) device id register (0x0005 ? silicon ? rev. e) protstart 0x00 0884 1 block protection start address register protrange 0x00 0885 1 block protection range address register reserved 0x00 0886 0x00 09ff 378 3.5 external interface, xintf (2812 only) this section gives a top-level view of the external interface (xintf) that is implemented on the 2812 devices. the external interface is a non-multiplexed asynchronous bus, similar to the c240x external interface. the external interface on the 2812 is mapped into five fixed zones shown in figure 3?5. figure 3?5 shows the 2812 xintf signals. functional overview 44 april 2001 ? revised december 2004 sprs174l xd(15:0) xa(18:0) xzcs6 xzcs7 xzcs6and7 xzcs2 xwe xr/w xready xmp/mc xhold xholda xclkout (see note e) xrd xintf zone 0 (8k 16) xintf zone 1 (8k 16) xintf zone 6 (512k 16) xintf zone 7 (16k 16) (mapped here if mp/mc = 1) 0x40 0000 0x3f c000 0x18 0000 0x10 0000 0x00 6000 0x00 4000 0x00 2000 0x00 0000 data space prog space xintf zone 2 (512k 16) 0x08 0000 notes: a. the mapping of xintf zone 7 is dependent on the xmp/mc device input signal and the mp/mc mode bit (bit 8 of xintcnf2 register). zones 0, 1, 2, and 6 are always enabled. b. each zone can be programmed with different wait states, setup and hold timing, and is supported by zone chip selects (xzcs0and1 , xzcs2 , xzcs6and7 ), which toggle when an access to a particular zone is performed. these features enable glueless connection to many external memories and peripherals. c. the chip selects for zone 0 and 1 are anded internally together to form one chip select (xzcs0and1 ). any external memory that is connected to xzcs0and1 is dually mapped to both zones 0 and zone 1. d. the chip selects for zone 6 and 7 are anded internally together to form one chip select (xzcs6and7 ). any external memory that is connected to xzcs6and7 is dually mapped to both zones 6 and zone 7. this means that if zone 7 is disabled (via the mp/mc mode) then any external memory is still accessible via zone 6 address space. e. xclkout is also pinned out on the 2810 and 2811. xzcs0and1 xzcs0 xzcs1 figure 3?5. external interface block diagram functional overview 45 april 2001 ? revised december 2004 sprs174l the operation and timing of the external interface, can be controlled by the registers listed in table 3?9. table 3?9. xintf configuration and control register mappings name address size (x16) description xtiming0 0x00 0b20 2 xintf timing register , zone 0 can access as two 16-bit registers or one 32-bit register xtiming1 0x00 0b22 2 xintf timing register , zone 1 can access as two 16-bit registers or one 32-bit register xtiming2 0x00 0b24 2 xintf timing register , zone 2 can access as two 16-bit registers or one 32-bit register xtiming6 0x00 0b2c 2 xintf timing register , zone 6 can access as two 16-bit registers or one 32-bit register xtiming7 0x00 0b2e 2 xintf timing register , zone 7 can access as two 16-bit registers or one 32-bit register xintcnf2 0x00 0b34 2 xintf configuration register can access as two 16-bit registers or one 32-bit register xbank 0x00 0b38 1 xintf bank control register xrevision 0x00 0b3a 1 xintf revision register 3.5.1 timing registers xintf signal timing can be tuned to match specific external device requirements such as setup and hold times to strobe signals for contention avoidance and maximizing bus efficiency. the timing parameters can be configured individually for each zone. this allows the programmer to maximize the efficiency of the bus, based on the type of memory or peripheral that the user needs to access. all xintf timing values are with respect to xtimclk, which is equal to or one-half of the sysclkout rate, as shown in figure 6?29. for detailed information on the xintf timing and configuration register bit fields, see the tms320x281x dsp external interface (xintf) reference guide (literature number spru067). 3.5.2 xrevision register the xrevision register contains a unique number to identify the particular version of xintf used in the product. for the 2812, this register will be configured as described in table 3?10. table 3?10. xrevision register bit definitions bit(s) name type reset description 15?0 revision r 0x0004 current xintf revision. for internal use/reference. test purposes only. subject to change. functional overview 46 april 2001 ? revised december 2004 sprs174l 3.6 interrupts figure 3?6 shows how the various interrupt sources are multiplexed within the f281x and c281x devices. c28x cpu pie timer 2 (for rtos) timer 0 watchdog peripherals (spi, sci, mcbsp, can, ev, adc) (41 interrupts) 96 interrupts ? tint0 interrupt control xnmicr(15:0) xint1 interrupt control xint1cr(15:0) xint2 interrupt control xint2cr(15:0) gpio mux wdint int1 to int12 int13 int14 nmi xint1ctr(15:0) xint2ctr(15:0) xnmictr(15:0) timer 1 (for rtos) tint2 low-power modes lpmint wakeint xnmi_xint13 mux tint1 enable select ? out of a possible 96 interrupts, 45 are currently used by peripherals. figure 3?6. interrupt sources eight pie block interrupts are grouped into one cpu interrupt. in total, 12 cpu interrupt groups, with 8 interrupts per group equals 96 possible interrupts. on the f281x and c281x, 45 of these are used by peripherals as shown in table 3?11. functional overview 47 april 2001 ? revised december 2004 sprs174l int12 mux int11 int2 int1 cpu (enable) (flag) intx intx.8 pieierx(8:1) pieifrx(8:1) mux intx.7 intx.6 intx.5 intx.4 intx.3 intx.2 intx.1 from peripherals or external interrupts (enable) (flag) ier(12:1) ifr(12:1) global enable intm 1 0 pieackx (enable/flag) figure 3?7. multiplexing of interrupts using the pie block table 3?11. pie peripheral interrupts ? cpu pie interrupts cpu interrupts intx.8 intx.7 intx.6 intx.5 intx.4 intx.3 intx.2 intx.1 int1 wakeint (lpm/wd) tint0 (timer 0) adcint (adc) xint2 xint1 reserved pdpintb (ev-b) pdpinta (ev-a) int2 reserved t1ofint (ev-a) t1ufint (ev-a) t1cint (ev-a) t1pint (ev-a) cmp3int (ev-a) cmp2int (ev-a) cmp1int (ev-a) int3 reserved capint3 (ev-a) capint2 (ev-a) capint1 (ev-a) t2ofint (ev-a) t2ufint (ev-a) t2cint (ev-a) t2pint (ev-a) int4 reserved t3ofint (ev-b) t3ufint (ev-b) t3cint (ev-b) t3pint (ev-b) cmp6int (ev-b) cmp5int (ev-b) cmp4int (ev-b) int5 reserved capint6 (ev-b) capint5 (ev-b) capint4 (ev-b) t4ofint (ev-b) t4ufint (ev-b) t4cint (ev-b) t4pint (ev-b) int6 reserved reserved mxint (mcbsp) mrint (mcbsp) reserved reserved spitxinta (spi) spirxinta (spi) int7 reserved reserved reserved reserved reserved reserved reserved reserved int8 reserved reserved reserved reserved reserved reserved reserved reserved int9 reserved reserved ecan1int (can) ecan0int (can) scitxintb (sci-b) scirxintb (sci-b) scitxinta (sci-a) scirxinta (sci-a) int10 reserved reserved reserved reserved reserved reserved reserved reserved int11 reserved reserved reserved reserved reserved reserved reserved reserved int12 reserved reserved reserved reserved reserved reserved reserved reserved ? out of the 96 possible interrupts, 45 interrupts are currently used. the remaining interrupts are reserved for future devices. these interrupts can be used as software interrupts if they are enabled at the pieifrx level, provided none of the interrupts within the group i s being used by a peripheral. otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the pieifr. to summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: 1) no peripheral within the group is asserting interrupts. 2) no peripheral interrupts are assigned to the group (example pie group 12). functional overview 48 april 2001 ? revised december 2004 sprs174l table 3?12. pie configuration and control registers name address size (x16) description piectrl 0x0000?0ce0 1 pie, control register pieack 0x0000?0ce1 1 pie, acknowledge register pieier1 0x0000?0ce2 1 pie, int1 group enable register pieifr1 0x0000?0ce3 1 pie, int1 group flag register pieier2 0x0000?0ce4 1 pie, int2 group enable register pieifr2 0x0000?0ce5 1 pie, int2 group flag register pieier3 0x0000?0ce6 1 pie, int3 group enable register pieifr3 0x0000?0ce7 1 pie, int3 group flag register pieier4 0x0000?0ce8 1 pie, int4 group enable register pieifr4 0x0000?0ce9 1 pie, int4 group flag register pieier5 0x0000?0cea 1 pie, int5 group enable register pieifr5 0x0000?0ceb 1 pie, int5 group flag register pieier6 0x0000?0cec 1 pie, int6 group enable register pieifr6 0x0000?0ced 1 pie, int6 group flag register pieier7 0x0000?0cee 1 pie, int7 group enable register pieifr7 0x0000?0cef 1 pie, int7 group flag register pieier8 0x0000?0cf0 1 pie, int8 group enable register pieifr8 0x0000?0cf1 1 pie, int8 group flag register pieier9 0x0000?0cf2 1 pie, int9 group enable register pieifr9 0x0000?0cf3 1 pie, int9 group flag register pieier10 0x0000?0cf4 1 pie, int10 group enable register pieifr10 0x0000?0cf5 1 pie, int10 group flag register pieier11 0x0000?0cf6 1 pie, int11 group enable register pieifr11 0x0000?0cf7 1 pie, int11 group flag register pieier12 0x0000?0cf8 1 pie, int12 group enable register pieifr12 0x0000?0cf9 1 pie, int12 group flag register reserved 0x0000?0cfa 0x0000?0cff 6 reserved note: the pie configuration and control registers are not protected by eallow mode. the pie vector table is protected. functional overview 49 april 2001 ? revised december 2004 sprs174l 3.6.1 external interrupts table 3?13. external interrupts registers name address size (x16) description xint1cr 0x00 7070 1 xint1 control register xint2cr 0x00 7071 1 xint2 control register reserved 0x00 7072 0x00 7076 5 xnmicr 0x00 7077 1 xnmi control register xint1ctr 0x00 7078 1 xint1 counter register xint2ctr 0x00 7079 1 xint2 counter register reserved 0x00 707a 0x00 707e 5 xnmictr 0x00 707f 1 xnmi counter register each external interrupt can be enabled/disabled or qualified using positive or negative going edge. for more information, see the tms320x281x system control and interrupts reference guide (literature number spru078). functional overview 50 april 2001 ? revised december 2004 sprs174l 3.7 system control this section describes the f281x and c281x oscillator, pll and clocking mechanisms, the watchdog function and the low power modes. figure 3?8 shows the various clock and reset domains in the f281x and c281x devices that will be discussed. hspclk pll x1/xclkin x2 power modes control watchdog block c28x cpu peripheral bus low-speed peripherals sci-a/b, spi, mcbsp peripheral registers high-speed peripherals ev-a/b high-speed prescaler low-speed prescaler clock enables gpio mux system control registers peripheral registers xf_xplldis adc registers 12-bit adc 16 adc inputs hspclk lspclk i/o i/o peripheral reset sysclkout xrs reset gpios ecan peripheral registers i/o osc clkin note a: clkin is the clock input to the cpu. sysclkout is the output clock of the cpu. they are of the same frequency. (see note a) figure 3?8. clock and reset domains functional overview 51 april 2001 ? revised december 2004 sprs174l the pll, clocking, watchdog and low-power modes, are controlled by the registers listed in table 3?14. table 3?14. pll, clocking, watchdog, and low-power mode registers ? name address size (x16) description reserved 0x00 7010 0x00 7017 8 reserved 0x00 7018 1 reserved 0x00 7019 1 hispcp 0x00 701a 1 high-speed peripheral clock prescaler register for hspclk clock lospcp 0x00 701b 1 low-speed peripheral clock prescaler register for lspclk clock pclkcr 0x00 701c 1 peripheral clock control register reserved 0x00 701d 1 lpmcr0 0x00 701e 1 low power mode control register 0 lpmcr1 0x00 701f 1 low power mode control register 1 reserved 0x00 7020 1 pllcr 0x00 7021 1 pll control register ? scsr 0x00 7022 1 system control & status register wdcntr 0x00 7023 1 watchdog counter register reserved 0x00 7024 1 wdkey 0x00 7025 1 watchdog reset key register reserved 0x00 7026 0x00 7028 3 wdcr 0x00 7029 1 watchdog control register reserved 0x00 702a 0x00 702f 6 ? all of the above registers can only be accessed, by executing the eallow instruction. ? the pll control register (pllcr) is reset to a known state by the xrs signal only. emulation reset (through code composer studio) will not reset pllcr. functional overview 52 april 2001 ? revised december 2004 sprs174l 3.8 osc and pll block figure 3?9 shows the osc and pll block on the f281x and c281x. x2 x1/xclkin on-chip oscillator (osc) pll bypass /2 xf_xplldis oscclk (pll disabled) latch xplldis xrs pll 4-bit pll select sysclkou t 1 0 clkin cpu 4-bit pll select xclkin pll block figure 3?9. osc and pll block the on-chip oscillator circuit enables a crystal to be attached to the f281x and c281x devices using the x1/xclkin and x2 pins. if a crystal is not used, then an external oscillator can be directly connected to the x1/xclkin pin and the x2 pin is left unconnected. the logic-high level in this case should not exceed v dd . the pllcr bits [3:0] set the clocking ratio. table 3?15. pllcr register bit definitions bit(s) name type xrs reset ? description 15:4 reserved r = 0 0:0 3:0 div r/w 0,0,0,0 sysclkout = (xclkin * n)/2, where n is the pll multiplication factor. bit value n sysclkout 0000 pll bypassed xclkin/2 0001 1 xclkin/2 0010 2 xclkin 0011 3 xclkin * 1.5 0100 4 xclkin * 2 0101 5 xclkin * 2.5 0110 6 xclkin * 3 0111 7 xclkin * 3.5 1000 8 xclkin * 4 1001 9 xclkin * 4.5 1010 10 xclkin * 5 1011 11 reserved 1100 12 reserved 1101 13 reserved 1110 14 reserved 1111 15 reserved ? the pllcr register is reset to a known state by the xrs reset line. if a reset is issued by the debugger, the pll clocking ratio is not changed. functional overview 53 april 2001 ? revised december 2004 sprs174l 3.8.1 loss of input clock in pll enabled mode, if the input clock xclkin or the oscillator clock is removed or absent, the pll will still issue a ?limp-mode? clock. the limp-mode clock will continue to clock the cpu and peripherals at a typical frequency of 1?4 mhz. the pllcr register should have been written to with a non-zero value for this feature to work. normally, when the input clocks are present, the watchdog counter will decrement to initiate a watchdog reset or wdint interrupt. however, when the external input clock fails, the watchdog counter will stop decrementing (i.e., the watchdog counter does not change with the limp-mode clock). this condition could be used by the application firmware to detect the input clock failure and initiate necessary shut-down procedure for the system. 3.9 pll-based clock module the f281x and c281x have an on-chip, pll-based clock module. this module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. the pll has a 4-bit ratio control to select different cpu clock rates. the watchdog module should be disabled before writing to the pllcr register. it can be re-enabled (if need be) after the pll module has stabilized, which takes 131 072 xclkin cycles. the pll-based clock module provides two modes of operation: ? crystal-operation this mode allows the use of an external crystal/resonator to provide the time base to the device. ? external clock source operation this mode allows the internal oscillator to be bypassed. the device clocks are generated from an external clock source input on the x1/xclkin pin. external clock signal (toggling 0 ?v dd ) c l1 (see note a) x2 x1/xclkin x1/xclkin x2 crystal c l2 (see note a) (a) (b) nc note a: ti recommends that customers have the resonator/crystal vendor characterize the operation of their device with the dsp c hip. the resonator/crystal vendor has the equipment and expertise to tune the tank circuit. the vendor can also advise the customer rega rding the proper tank component values that will ensure start-up and stability over the entire operating range. figure 3?10. recommended crystal / clock connection table 3?16. possible pll configuration modes pll mode remarks sysclkout pll disabled invoked by tying xplldis pin low upon reset. pll block is completely disabled. clock input to the cpu (clkin) is directly derived from the clock signal present at the x1/xclkin pin. xclkin pll bypassed default pll configuration upon power-up, if pll is not disabled. the pll itself is bypassed. however, the /2 module in the pll block divides the clock input at the x1/xclkin pin by two before feeding it to the cpu. xclkin/2 pll enabled achieved by writing a non-zero value ?n? into pllcr register. the /2 module in the pll block now divides the output of the pll by two before feeding it to the cpu. (xclkin * n) / 2 functional overview 54 april 2001 ? revised december 2004 sprs174l 3.10 external reference oscillator clock option the typical specifications for the external quartz crystal for a frequency of 30 mhz are listed below: ? fundamental mode, parallel resonant ? c l (load capacitance) = 12 pf ? c l1 = c l2 = 24 pf ? c shunt = 6 pf ? esr range = 25 to 40 ? 3.11 watchdog block the watchdog block on the f281x and c281x is identical to the one used on the 240x devices. the watchdog module generates an output pulse, 512 oscillator clocks wide (oscclk), whenever the 8-bit watchdog up counter has reached its maximum value. to prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xaa sequence into the watchdog key register which will reset the watchdog counter. figure 3?11 shows the various functional blocks within the watchdog module. /512 oscclk wdcr (wdps(2:0)) wdclk wdcntr(7:0) wdkey(7:0) bad key good key 1 0 1 wdcr (wdchk(2:0)) bad wdchk key wdcr (wddis) clear counter scsr (wdenint) watchdog prescaler generate output pulse (512 oscclks) 8-bit watchdog counter clr wdrst wdint watchdog 55 + aa key detector xrs core-reset note a: the wdrst signal is driven low for 512 oscclk cycles. wdrst (see note a) internal pullup figure 3?11. watchdog module the wdint signal enables the watchdog to be used as a wakeup from idle/standby mode timer. in standby mode, all peripherals are turned off on the device. the only peripheral that remains functional is the watchdog. the watchdog module will run off the pll clock or the oscillator clock. the wdint signal is fed to the lpm block so that it can wake the device from standby (if enabled). see section 3.12, low-power modes block, for more details. functional overview 55 april 2001 ? revised december 2004 sprs174l in idle mode, the wdint signal can generate an interrupt to the cpu, via the pie, to take the cpu out of idle mode. in halt mode, this feature cannot be used because the oscillator (and pll) are turned off and hence so is the watchdog. 3.12 low-power modes block the low-power modes on the f281x and c281x are similar to the 240x devices. table 3?17 summarizes the various modes. table 3?17. f281x and c281x low-power modes mode lpm(1:0) oscclk clkin sysclkout exit ? normal x,x on on on ? idle 0,0 on on on ? xrs , wdint , any enabled interrupt, xnmi debugger standby 0,1 on (watchdog still running) off off xrs , wdint , xint1 , xnmi , t1/2/3/4ctrip , c1/2/3/4/5/6trip , scirxda, scirxdb, canrx, debugger halt 1,x off (oscillator and pll turned off, watchdog not functional) off off xrs , xnmi , debugger ? the exit column lists which signals or under what conditions the low power mode will be exited. a low signal, on any of the sig nals, will exit the low power condition. this signal must be kept low long enough for an interrupt to be recognized by the device. otherwise the id le mode will not be exited and the device will go back into the indicated low power mode. ? the idle mode on the c28x behaves dif ferently than on the 24x/240x. on the c28x, the clock output from the core (sysclkout) is still functional while on the 24x/240x the clock is turned off. on the c28x, the jtag port can still function even if the core clock (clkin) is turned off. the various low-power modes operate as follows: idle mode: this mode is exited by any enabled interrupt or an xnmi that is recognized by the processor. the lpm block performs no tasks during this mode as long as the lpmcr0(lpm) bits are set to 0,0. standby mode: all other signals (including xnmi) will wake the device from st andby mode if selected by the lpmcr1 register. the user will need to select which signal(s) will wake the device. the selected signal(s) are also qualified by the oscclk before waking the device. the number of oscclks is specified in the lpmcr0 register. halt mode: only the xrs and xnmi external signals can wake the device from halt mode. the xnmi input to the core has an enable/disable bit. hence, it is safe to use the xnmi signal for this function. note: the low-power modes do not affect the state of the output pins (pwm pins included). they will be in whatever state the code left them in when the idle instruction was executed. peripherals 56 april 2001 ? revised december 2004 sprs174l 4 peripherals the integrated peripherals of the f281x and c281x are described in the following subsections: ? three 32-bit cpu-timers ? two event-manager modules (eva, evb) ? enhanced analog-to-digital converter (adc) module ? enhanced controller area network (ecan) module ? multichannel buffered serial port (mcbsp) module ? serial communications interface modules (sci-a, sci-b) ? serial peripheral interface (spi) module ? digital i/o and shared pin functions 4.1 32-bit cpu-timers 0/1/2 there are three 32-bit cpu-timers on the f281x and c281x devices (cpu-timer0/1/2). cpu-timer 1 is reserved for ti system functions and timer 2 is reserved for dsp/bios. cpu-t imer 0 can be used in user applications. these timers are different from the general-purpose (gp) timers that are present in the event manager modules (eva, evb). note: if the application is not using dsp/bios, then cpu-timers 1 and 2 can be used in the application. borrow reset timer reload sysclkout tcr.4 (timer start status) tint 16-bit timer divide-down tddrh:tddr 32-bit timer period prdh:prd 32-bit counter timh:tim 16-bit prescale counter psch:psc borrow figure 4?1. cpu-timers peripherals 57 april 2001 ? revised december 2004 sprs174l in the f281x and c281x devices, the timer interrupt signals (tint0 , tint1 , tint2 ) are connected as shown in figure 4?2. int1 to int12 int14 c28x tint2 tint0 pie cpu-timer 0 cpu-timer 2 (reserved for dsp/bios) int13 tint1 cpu-timer 1 (reserved for ti system functions) xint13 notes: a. the timer registers are connected to the memory bus of the c28x processor. b. the timing of the timers is synchronized to sysclkout of the processor clock. figure 4?2. cpu-timer interrupts signals and output signal (see notes a and b) the general operation of the timer is as follows: the 32-bit counter register ?timh:tim? is loaded with the value in the period register ?prdh:prd?. the counter register, decrements at the sysclkout rate of the c28x. when the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. the registers listed in table 4?1 are used to configure the timers. for more information, see the tms320x281x system control and interrupts reference guide (literature number spru078). peripherals 58 april 2001 ? revised december 2004 sprs174l table 4?1. cpu-timers 0, 1, 2 configuration and control registers name address size (x16) description timer0tim 0x00 0c00 1 cpu-timer 0, counter register timer0timh 0x00 0c01 1 cpu-timer 0, counter register high timer0prd 0x00 0c02 1 cpu-timer 0, period register timer0prdh 0x00 0c03 1 cpu-timer 0, period register high timer0tcr 0x00 0c04 1 cpu-timer 0, control register reserved 0x00 0c05 1 timer0tpr 0x00 0c06 1 cpu-timer 0, prescale register timer0tprh 0x00 0c07 1 cpu-timer 0, prescale register high timer1tim 0x00 0c08 1 cpu-timer 1, counter register timer1timh 0x00 0c09 1 cpu-timer 1, counter register high timer1prd 0x00 0c0a 1 cpu-timer 1, period register timer1prdh 0x00 0c0b 1 cpu-timer 1, period register high timer1tcr 0x00 0c0c 1 cpu-timer 1, control register reserved 0x00 0c0d 1 timer1tpr 0x00 0c0e 1 cpu-timer 1, prescale register timer1tprh 0x00 0c0f 1 cpu-timer 1, prescale register high timer2tim 0x00 0c10 1 cpu-timer 2, counter register timer2timh 0x00 0c11 1 cpu-timer 2, counter register high timer2prd 0x00 0c12 1 cpu-timer 2, period register timer2prdh 0x00 0c13 1 cpu-timer 2, period register high timer2tcr 0x00 0c14 1 cpu-timer 2, control register reserved 0x00 0c15 1 timer2tpr 0x00 0c16 1 cpu-timer 2, prescale register timer2tprh 0x00 0c17 1 cpu-timer 2, prescale register high reserved 0x00 0c18 0x00 0c3f 40 peripherals 59 april 2001 ? revised december 2004 sprs174l 4.2 event manager modules (eva, evb) the event-manager modules include general-purpose (gp) timers, full-compare/pwm units, capture units, and quadrature-encoder pulse (qep) circuits. eva and evb timers, compare units, and capture units function identically. however, timer/unit names differ for eva and evb. t able 4?2 shows the module and signal names used. t able 4?2 shows the features and functionality available for the event-manager modules and highlights eva nomenclature. event managers a and b have identical peripheral register sets with eva starting at 7400h and evb starting at 7500h. the paragraphs in this section describe the function of gp timers, compare units, capture units, and qeps using eva nomenclature. these paragraphs are applicable to evb with regard to function?however, module/signal names would differ. table 4?3 lists the eva registers. for more information, see the tms320x281x dsp event manager (ev) reference guide (literature number spru065). table 4?2. module and signal names for eva and evb event manager modules eva evb event manager modules module signal module signal gp timers gp timer 1 gp timer 2 t1pwm/t1cmp t2pwm/t2cmp gp timer 3 gp timer 4 t3pwm/t3cmp t4pwm/t4cmp compare units compare 1 compare 2 compare 3 pwm1/2 pwm3/4 pwm5/6 compare 4 compare 5 compare 6 pwm7/8 pwm9/10 pwm11/12 capture units capture 1 capture 2 capture 3 cap1 cap2 cap3 capture 4 capture 5 capture 6 cap4 cap5 cap6 qep channels qep1 qep2 qepi1 qep1 qep2 qep3 qep4 qepi2 qep3 qep4 external clock inputs direction external clock tdira tclkina direction external clock tdirb tclkinb external trip inputs compare c1trip c2trip c3trip compare c4trip c5trip c6trip external trip inputs t1ctrip_pdpinta ? t2ctrip /evasoc t3ctrip_pdpintb ? t4ctrip /evbsoc ? in the 24x/240x-compatible mode, the t1ctrip_pdpinta pin functions as pdpinta and the t3ctrip_pdpintb pin functions as pdpintb . peripherals 60 april 2001 ? revised december 2004 sprs174l table 4?3. eva registers ? name address size (x16) description gptcona 0x00 7400 1 gp timer control register a t1cnt 0x00 7401 1 gp timer 1 counter register t1cmpr 0x00 7402 1 gp timer 1 compare register t1pr 0x00 7403 1 gp timer 1 period register t1con 0x00 7404 1 gp timer 1 control register t2cnt 0x00 7405 1 gp timer 2 counter register t2cmpr 0x00 7406 1 gp timer 2 compare register t2pr 0x00 7407 1 gp timer 2 period register t2con 0x00 7408 1 gp timer 2 control register extcona ? 0x00 7409 1 gp extension control register a comcona 0x00 7411 1 compare control register a actra 0x00 7413 1 compare action control register a dbtcona 0x00 7415 1 dead-band timer control register a cmpr1 0x00 7417 1 compare register 1 cmpr2 0x00 7418 1 compare register 2 cmpr3 0x00 7419 1 compare register 3 capcona 0x00 7420 1 capture control register a capfifoa 0x00 7422 1 capture fifo status register a cap1fifo 0x00 7423 1 two-level deep capture fifo stack 1 cap2fifo 0x00 7424 1 two-level deep capture fifo stack 2 cap3fifo 0x00 7425 1 two-level deep capture fifo stack 3 cap1fbot 0x00 7427 1 bottom register of capture fifo stack 1 cap2fbot 0x00 7428 1 bottom register of capture fifo stack 2 cap3fbot 0x00 7429 1 bottom register of capture fifo stack 3 evaimra 0x00 742c 1 interrupt mask register a evaimrb 0x00 742d 1 interrupt mask register b evaimrc 0x00 742e 1 interrupt mask register c evaifra 0x00 742f 1 interrupt flag register a evaifrb 0x00 7430 1 interrupt flag register b evaifrc 0x00 7431 1 interrupt flag register c ? the ev-b register set is identical except the address range is from 0x00?7500 to 0x00?753f. the above registers are mapped to z one 2. this space allows only 16-bit accesses. 32-bit accesses produce undefined results. ? new register compared to 24x/240x peripherals 61 april 2001 ? revised december 2004 sprs174l gptcona(12:4), capcona(8), extcona[0] evato adc (internal) timer 1 compare output logic t1pwm_t1cmp gptcona(1,0) t1con(1) gp timer 1 tclkina prescaler hspclk t1con(10:8) t1con(5,4) clock full compare 1 full compare 2 full compare 3 svpwm state machine dead- band logic output logic pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 t1con(15:11,6,3,2) tdira dir timer 2 compare gp timer 2 16 capture units comcona(15:5,2:0) t1ctrip/pdpinta , t2ctrip , c1trip , c2trip , c3trip output logic t2pwm_t2cmp gptcona(3,2) t2con(1) t2con(15:11,7,6,3,2,0) actra(15:12), comcona(12), t1con(13:11) capcona(10,9) 16 dbtcona(15:0) actra(11:0) tclkina prescaler hspclk t2con(10:8) t2con(5,4) clock dir capcona(15:12,7:0) cap1_qep1 cap2_qep2 cap3_qepi1 qep logic qepclk qepdir 16 16 reset evaenclk control logic peripheral bus tdira index qual extcona(1:2) note a: the evb module is similar to the eva module. 16 evasoc adc (external) figure 4?3. event manager a functional block diagram (see note a) peripherals 62 april 2001 ? revised december 2004 sprs174l 4.2.1 general-purpose (gp) timers there are two gp timers. the gp timer x (x = 1 or 2 for eva; x = 3 or 4 for evb) includes: ? a 16-bit timer, up-/down-counter, txcnt, for reads or writes ? a 16-bit timer-compare register, txcmpr (double-buffered with shadow register), for reads or writes ? a 16-bit timer-period register, txpr (double-buffered with shadow register), for reads or writes ? a 16-bit timer-control register,txcon, for reads or writes ? selectable internal or external input clocks ? a programmable prescaler for internal or external clock inputs ? control and interrupt logic, for four maskable interrupts: underflow , overflow , timer compare , and period interrupts ? a selectable direction input pin (tdirx) (to count up or down when directional up- / down-count mode is selected) the gp timers can be operated independently or synchronized with each other. the compare register associated with each gp timer can be used for compare function and pwm-waveform generation. there are three continuous modes of operations for each gp timer in up- or up / down-counting operations. internal or external input clocks with programmable prescaler are used for each gp timer. gp timers also provide the time base for the other event-manager submodules: gp timer 1 for all the compares and pwm circuits, gp timer 2/1 for the capture units and the quadrature-pulse counting operations. double-buffering of the period and compare registers allows programmable change of the timer (pwm) period and the compare/pwm pulse width as needed. 4.2.2 full-compare units there are three full-compare units on each event manager. these compare units use gp timer1 as the time base and generate six outputs for compare and pwm-waveform generation using programmable deadband circuit. the state of each of the six outputs is configured independently. the compare registers of the compare units are double-buffered, allowing programmable change of the compare/pwm pulse widths as needed. 4.2.3 programmable deadband generator deadband generation can be enabled/disabled for each compare unit output individually. the deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal. the output states of the deadband generator are configurable and changeable as needed by way of the double-buffered actrx register. 4.2.4 pwm waveform generation up to eight pwm waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three full-compare units with programmable deadbands , and two independent pwms by the gp-timer compares. 4.2.5 double update pwm mode the f281x and c281x event manager supports ?double update pwm mode.? this mode refers to a pwm operation mode in which the position of the leading edge and the position of the trailing edge of a pwm pulse are independently modifiable in each pwm period. to support this mode, the compare register that determines the position of the edges of a pwm pulse must allow (buffered) compare value update once at the beginning of a pwm period and another time in the middle of a pwm period. the compare registers in f281x and c281x event managers are all buffered and support three compare value reload/update (value in buffer becoming active) modes. these modes have earlier been documented as compare value reload conditions. the reload condition that supports double update pwm mode is reloaded on underflow (beginning of pwm period) or period (middle of pwm period). double update pwm mode can be achieved by using this condition for compare value reload. peripherals 63 april 2001 ? revised december 2004 sprs174l 4.2.6 pwm characteristics characteristics of the pwms are as follows: ? 16-bit registers ? wide range of programmable deadband for the pwm output pairs ? change of the pwm carrier frequency for pwm frequency wobbling as needed ? change of the pwm pulse widths within and after each pwm period as needed ? external-maskable power and drive-protection interrupts ? pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector pwm waveforms ? minimized cpu overhead using auto-reload of the compare and period registers ? the pwm pins are driven to a high-impedance state when the pdpintx pin is driven low and after pdpintx signal qualification. the pdpintx pin (after qualification) is reflected in bit 8 of the comconx register. ? pdpinta pin status is reflected in bit 8 of comcona register. ? pdpintb pin status is reflected in bit 8 of comconb register. ? extcon register bits provide options to individually trip control for each pwm pair of signals 4.2.7 capture unit the capture unit provides a logging function for different events or transitions. the values of the selected gp timer counter is captured and stored in the two-level-deep fifo stacks when selected transitions are detected on capture input pins, capx (x = 1, 2, or 3 for eva; and x = 4, 5, or 6 for evb). the capture unit consists of three capture circuits. ? capture units include the following features: ? one 16-bit capture control register, capconx (r/w) ? one 16-bit capture fifo status register, capfifox ? selection of gp timer 1/2 (for eva) or 3/4 (for evb) as the time base ? three 16-bit 2-level-deep fifo stacks, one for each capture unit ? three capture input pins (cap1/2/3 for eva, cap4/5/6 for evb)?one input pin per capture unit. [all inputs are synchronized with the device (cpu) clock. in order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. the input pins cap1/2 and cap4/5 can also be used as qep inputs to the qep circuit.] ? user-specified transition (rising edge, falling edge, or both edges) detection ? three maskable interrupt flags, one for each capture unit ? the capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture function. 4.2.8 quadrature-encoder pulse (qep) circuit two capture inputs (cap1 and cap2 for eva; cap4 and cap5 for evb) can be used to interface the on-chip qep circuit with a quadrature encoder pulse. full synchronization of these inputs is performed on-chip. direction or leading-quadrature pulse sequence is detected, and gp timer 2/4 is incremented or decremented by the rising and falling edges of the two input signals (four times the frequency of either input pulse). with extcona register bits, the eva qep circuit can use cap3 as a capture index pin as well. similarly, with extconb register bits, the evb qep circuit can use cap6 as a capture index pin. peripherals 64 april 2001 ? revised december 2004 sprs174l 4.2.9 external adc start-of-conversion eva/evb start-of-conversion (soc) can be sent to an external pin (evasoc /evbsoc ) for external adc interface. evasoc and evbsoc are muxed with t2ctrip and t4ctrip , respectively. 4.3 enhanced analog-to-digital converter (adc) module a simplified functional block diagram of the adc module is shown in figure 4?4. the adc module consists of a 12-bit adc with a built-in sample-and-hold (s / h) circuit. functions of the adc module include: ? 12-bit adc core with built-in s/h ? analog input: 0.0 v to 3.0 v (voltages above 3.0 v produce full-scale conversion results.) ? fast conversion rate: 80 ns at 25-mhz adc clock, 12.5 msps ? 16-channel, muxed inputs ? autosequencing capability provides up to 16 ?autoconversions? in a single session. each conversion can be programmed to select any 1 of 16 input channels ? sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i.e., two cascaded 8-state sequencers) ? sixteen result registers (individually addressable) to store conversion values ? the digital value of the input analog voltage is derived by: when input 0 v d igital value 0, digital value 4095 input analog voltage adclo 3 digital value 4096 input analog voltage adclo 3 , when 0 v < input < 3 v digital value 4095, when input 3 v ? multiple triggers as sources for the start-of-conversion (soc) sequence ? s/w ? software immediate start ? eva ? event manager a (multiple event sources within eva) ? evb ? event manager b (multiple event sources within evb) ? flexible interrupt control allows interrupt request on every end-of-sequence (eos) or every other eos ? sequencer can operate in ?start/stop? mode, allowing multiple ?time-sequenced triggers? to synchronize conversions ? eva and evb triggers can operate independently in dual-sequencer mode ? sample-and-hold (s/h) acquisition time window has separate prescale control the adc module in the f281x and c281x has been enhanced to provide flexible interface to event managers a and b. the adc interface is built around a fast, 12-bit adc module with a fast conversion rate of 80 ns at 25-mhz adc clock. the adc module has 16 channels, configurable as two independent 8-channel modules to service event managers a and b. the two independent 8-channel modules can be cascaded to form a 16-channel module. although there are multiple input channels and two sequencers, there is only one converter in the adc module. figure 4?4 shows the block diagram of the f281x and c281x adc module. the two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog mux. in the cascaded mode, the autosequencer functions as a single 16-channel sequencer. on each sequencer, once the conversion is complete, the selected channel value is stored in its respective result register. autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. this gives increased resolution over traditional single-sampled conversion results. peripherals 65 april 2001 ? revised december 2004 sprs174l result registers evb s/w adcsoc eva s/w sequencer 2 sequencer 1 soc soc adc control registers 70b7h 70b0h 70afh 70a8h result reg 15 result reg 8 result reg 7 result reg 1 result reg 0 module adc 12-bit analog mux adcina0 adcina7 adcinb0 adcinb7 system control block high-speed prescaler hspclk adcenclk c28x sysclkout s/h s/h figure 4?4. block diagram of the f281x and c281x adc module to obtain the specified accuracy of the adc, proper board layout is very critical. to the best extent possible, traces leading to the adcin pins should not run in close proximity to the digital signal paths. this is to minimize switching noise on the digital lines from getting coupled to the adc inputs. furthermore, proper isolation techniques must be used to isolate the adc module power pins ( v dda1 /v dda2 , av ddrefbg ) from the digital supply. figure 4?5 shows the adc pin connections for the f281x and c281x devices. notes: 1. the adc registers are accessed at the sysclkout rate. the internal timing of the adc module is controlled by the high-speed peripheral clock (hspclk). 2. the behavior of the adc module based on the state of the adcenclk and halt signals is as follows: adcenclk: on reset, this signal will be low. while reset is active-low (xrs ) the clock to the register will still function. this is necessary to make sure all registers and modes go into their default reset state. the analog module will however be in a low-power inactive state. as soon as reset goes high, then the clock to the registers will be disabled. when the user sets the adcenclk signal high, then the clocks to the registers will be enabled and the analog module will be enabled. there will be a certain time delay (ms range) before the adc is stable and can be used. halt: this signal only affects the analog module. it does not af fect the registers. if low , the adc module is powered. if high, the adc module goes into low-power mode. the halt mode will stop the clock to the cpu, which will stop the hspclk. therefore the adc register logic will be turned off indirectly. peripherals 66 april 2001 ? revised december 2004 sprs174l figure 4?5 shows the adc pin-biasing for internal reference and figure 4?6 shows the adc pin-biasing for external reference. adcina[7:0] adcinb[7:0] adclo adcbgrefin ? adc external current bias resistor adcresext adcrefp v dda1 v dda2 v ssa1 v ssa2 avddrefbg avssrefbg v ddaio v ssaio v dd1 v ss1 test pin adc reference positive output adcrefm adc reference medium output adc analog power adc reference power adc analog i/o power adc digital power analog input 0?3 v with respect to adclo connect to analog ground 24.9 k /20 k (see note c) 10 f ? 10 f ? analog 3.3 v analog 3.3 v analog 3.3 v analog 3.3 v analog ground 1.8 v adcrefp and adcrefm should not be loaded by external circuitry can use the same 1.8 v (or 1.9 v) supply as the digital core but separate the two with a ferrite bead or a filter digital ground adc 16-channel analog inputs ? provide access to this pin in pcb layouts. intended for test purposes only. ? taiyo yuden emk325f106zh, emk325bj106md, or equivalent notes: a. external decoupling capacitors are recommended on all power pins. b. analog inputs must be driven from an operational amplifier that does not degrade the adc performance. c. use 24.9 k ? for adc clock range 1 ? 18.75 mhz; use 20 k ? for adc clock range 18.75 ? 25 mhz. figure 4?5. adc pin connections with internal reference (see notes a and b) note: the temperature rating of any recommended component must match the rating of the end product. peripherals 67 april 2001 ? revised december 2004 sprs174l adcina[7:0] adcinb[7:0] adclo adcbgrefin adc external current bias resistor adcresext adcrefp v dda1 v dda2 v ssa1 v ssa2 avddrefbg avssrefbg v ddaio v ssaio v dd1 v ss1 test pin adc reference positive input adcrefm adc reference medium input adc analog power adc reference power adc analog i/o power adc digital power analog input 0?3 v with respect to adclo connect to analog ground 24.9 k 20 k (see note c) analog 3.3 v analog 3.3 v analog 3.3 v analog 3.3 v analog ground 1.8 v can use the same 1.8-v (or 1.9-v) supply as the digital core but separate the two with a ferrite bead or a filter digital ground adc 16-channel analog inputs 1 f ?10 f 2 v 1 v 1 f ? 10 f notes: a. external decoupling capacitors are recommended on all power pins. b. analog inputs must be driven from an operational amplifier that does not degrade the adc performance. c. use 24.9 k ? for adc clock range 1 ? 18.75 mhz; use 20 k ? for adc clock range 18.75 ? 25 mhz. d. it is recommended that buf fered external references be provided with a voltage difference of (adcrefp-adcrefm) = 1 v 0.1% or better. external reference is enabled using bit 8 in the adctrl3 register at adc power up. in this mode, the accuracy of external reference is critical for overall gain. the voltage adcrefp?adcrefm will determine the overall accuracy. do not enable internal references when external references are connected to adcrefp and adcrefm. see the tms320x281x dsp analog-to-digital converter (adc) reference guide (literature number spru060) for more information. (see note d) figure 4?6. adc pin connections with external reference peripherals 68 april 2001 ? revised december 2004 sprs174l the adc operation is configured, controlled, and monitored by the registers listed in table 4?4. table 4?4. adc registers ? name address size (x16) description adctrl1 0x00 7100 1 adc control register 1 adctrl2 0x00 7101 1 adc control register 2 adcmaxconv 0x00 7102 1 adc maximum conversion channels register adcchselseq1 0x00 7103 1 adc channel select sequencing control register 1 adcchselseq2 0x00 7104 1 adc channel select sequencing control register 2 adcchselseq3 0x00 7105 1 adc channel select sequencing control register 3 adcchselseq4 0x00 7106 1 adc channel select sequencing control register 4 adcaseqsr 0x00 7107 1 adc auto-sequence status register adcresult0 0x00 7108 1 adc conversion result buffer register 0 adcresult1 0x00 7109 1 adc conversion result buffer register 1 adcresult2 0x00 710a 1 adc conversion result buffer register 2 adcresult3 0x00 710b 1 adc conversion result buffer register 3 adcresult4 0x00 710c 1 adc conversion result buffer register 4 adcresult5 0x00 710d 1 adc conversion result buffer register 5 adcresult6 0x00 710e 1 adc conversion result buffer register 6 adcresult7 0x00 710f 1 adc conversion result buffer register 7 adcresult8 0x00 7110 1 adc conversion result buffer register 8 adcresult9 0x00 7111 1 adc conversion result buffer register 9 adcresult10 0x00 7112 1 adc conversion result buffer register 10 adcresult11 0x00 7113 1 adc conversion result buffer register 11 adcresult12 0x00 7114 1 adc conversion result buffer register 12 adcresult13 0x00 7115 1 adc conversion result buffer register 13 adcresult14 0x00 7116 1 adc conversion result buffer register 14 adcresult15 0x00 7117 1 adc conversion result buffer register 15 adctrl3 0x00 7118 1 adc control register 3 adcst 0x00 7119 1 adc status register reserved 0x00 711c 0x00 711f 4 ? the above registers are peripheral frame 2 registers. peripherals 69 april 2001 ? revised december 2004 sprs174l 4.4 enhanced controller area network (ecan) module the can module has the following features: ? fully compliant with can protocol, version 2.0b ? supports data rates up to 1 mbps ? thirty-two mailboxes, each with the following properties: ? configurable as receive or transmit ? configurable with standard or extended identifier ? has a programmable receive mask ? supports data and remote frame ? composed of 0 to 8 bytes of data ? uses a 32-bit time stamp on receive and transmit message ? protects against reception of new message ? holds the dynamically programmable priority of transmit message ? employs a programmable interrupt scheme with two interrupt levels ? employs a programmable alarm on transmission or reception time-out ? low-power mode ? programmable wake-up on bus activity ? automatic reply to a remote request message ? automatic retransmission of a frame in case of loss of arbitration or error ? 32-bit local network time counter synchronized by a specific message (communication in conjunction with mailbox 16) ? self-test mode ? operates in a loopback mode receiving its own message. a ?dummy? acknowledge is provided, thereby eliminating the need for another node to provide the acknowledge bit. note: for a sysclkout of 150 mhz, the smallest bit rate possible is 23.4 kbps. the 28x can has passed the conformance test per iso/dis 16845. contact ti for further details. peripherals 70 april 2001 ? revised december 2004 sprs174l mailbox ram (512 bytes) 32-message mailbox of 4 32-bit words memory management unit cpu interface, receive control unit, timer management unit ecan memory (512 bytes) registers and message objects control 32 32 message controller 32 32 32 32 32 32 ecan protocol kernel receive buffer transmit buffer control buffer status buffer enhanced can controller 32 controls address data ecan1int ecan0int 32 sn65hvd23x 3.3-v can transceiver can bus figure 4?7. ecan block diagram and interface circuit table 4?5. 3.3-v ecan transceivers for the tms320f281x and tms320c281x dsps part number supply voltage low-power mode slope control vref other t a sn65hvd230 3.3 v standby adjustable yes ?? ?40 c to 85 c sn65hvd230q 3.3 v standby adjustable yes ?? ?40 c to 125 c sn65hvd231 3.3 v sleep adjustable yes ?? ?40 c to 85 c sn65hvd231q 3.3 v sleep adjustable yes ?? ?40 c to 125 c sn65hvd232 3.3 v none none none ?? ?40 c to 85 c sn65hvd232q 3.3 v none none none ?? ?40 c to 125 c sn65hvd233 3.3 v standby adjustable none diagnostic loopback ?40 c to 125 c sn65hvd234 3.3 v standby & sleep adjustable none ?? ?40 c to 125 c sn65hvd235 3.3 v standby adjustable none autobaud loopback ?40 c to 125 c peripherals 71 april 2001 ? revised december 2004 sprs174l mailbox enable ? canme mailbox direction ? canmd transmission request set ? cantrs transmission request reset ? cantrr transmission acknowledge ? canta abort acknowledge ? canaa received message pending ? canrmp received message lost ? canrml remote frame pending ? canrfp global acceptance mask ? cangam master control ? canmc bit-timing configuration ? canbtc error and status ? canes transmit error counter ? cantec receive error counter ? canrec global interrupt flag 0 ? cangif0 global interrupt mask ? cangim mailbox interrupt mask ? canmim mailbox interrupt level ? canmil overwrite protection control ? canopc tx i/o control ? cantioc rx i/o control ? canrioc time stamp counter ? cantsc global interrupt flag 1 ? cangif1 time-out control ? cantoc time-out status ? cantos reserved ecan control and status registers message identifier ? msgid 61e8h?61e9h message control ? msgctrl message data low ? mdl message data high ? mdh message mailbox (16 bytes) control and status registers 6000h 603fh local acceptance masks (lam) (32 32-bit ram) 6040h 607fh 6080h 60bfh 60c0h 60ffh ecan memory (512 bytes) message object time stamps (mots) (32 32-bit ram) message object time-out (moto) (32 32-bit ram) mailbox 0 6100h?6107h mailbox 1 6108h?610fh mailbox 2 6110h?6117h mailbox 3 6118h?611fh ecan memory ram (512 bytes) mailbox 4 6120h?6127h mailbox 28 61e0h?61e7h mailbox 29 61e8h?61efh mailbox 30 61f0h?61f7h mailbox 31 61f8h?61ffh 61eah?61ebh 61ech?61edh 61eeh?61efh figure 4?8. ecan memory map peripherals 72 april 2001 ? revised december 2004 sprs174l the can registers listed in table 4?6 are used by the cpu to configure and control the can controller and the message objects. ecan control registers only support 32-bit read/write operations. mailbox ram can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. table 4?6. can registers map ? register name address size (x32) description canme 0x00 6000 1 mailbox enable canmd 0x00 6002 1 mailbox direction cantrs 0x00 6004 1 transmit request set cantrr 0x00 6006 1 transmit request reset canta 0x00 6008 1 transmission acknowledge canaa 0x00 600a 1 abort acknowledge canrmp 0x00 600c 1 receive message pending canrml 0x00 600e 1 receive message lost canrfp 0x00 6010 1 remote frame pending cangam 0x00 6012 1 global acceptance mask canmc 0x00 6014 1 master control canbtc 0x00 6016 1 bit-timing configuration canes 0x00 6018 1 error and status cantec 0x00 601a 1 transmit error counter canrec 0x00 601c 1 receive error counter cangif0 0x00 601e 1 global interrupt flag 0 cangim 0x00 6020 1 global interrupt mask cangif1 0x00 6022 1 global interrupt flag 1 canmim 0x00 6024 1 mailbox interrupt mask canmil 0x00 6026 1 mailbox interrupt level canopc 0x00 6028 1 overwrite protection control cantioc 0x00 602a 1 tx i/o control canrioc 0x00 602c 1 rx i/o control cantsc 0x00 602e 1 time stamp counter (reserved in scc mode) cantoc 0x00 6030 1 time-out control (reserved in scc mode) cantos 0x00 6032 1 time-out status (reserved in scc mode) ? these registers are mapped to peripheral frame 1. peripherals 73 april 2001 ? revised december 2004 sprs174l 4.5 multichannel buffered serial port (mcbsp) module the mcbsp module has the following features: ? compatible to mcbsp in tms320c54x ? /tms320c55x ? dsp devices, except the dma features ? full-duplex communication ? double-buffered data registers which allow a continuous data stream ? independent framing and clocking for receive and transmit ? external shift clock generation or an internal programmable frequency shift clock ? a wide selection of data sizes including 8-, 12-, 16-, 20-, 24-, or 32-bits ? 8-bit data transfers with lsb or msb first ? programmable polarity for both frame synchronization and data clocks ? highly programmable internal clock and frame generation ? support a-bis mode ? direct interface to industry-standard codecs, analog interface chips (aics), and other serially connected a/d and d/a devices ? works with spi-compatible devices ? two 16 x 16-level fifo for transmit channel ? two 16 x 16-level fifo for receive channel the following application interfaces can be supported on the mcbsp: ? t1/e1 framers ? mvip switching-compatible and st-bus-compliant devices including: ? mvip framers ? h.100 framers ? scsa framers ? iom-2 compliant devices ? ac97-compliant devices (the necessary multiphase frame synchronization capability is provided.) ? iis-compliant devices ? mcbsp clock rate = clkg = clksrg (1 clkgdiv) , where clksrg source could be lspclk, clkx, or clkr. ? tms320c54x and tms320c55x are trademarks of texas instruments. ? serial port performance is limited by i/o buffer switching speed. internal prescalers must be adjusted such that the peripheral speed is less than the i/o buffer speed limit?20-mhz maximum. peripherals 74 april 2001 ? revised december 2004 sprs174l figure 4?9 shows the block diagram of the mcbsp module with fifo, interfaced to the f281x and c281x version of peripheral frame 2. mcbsp receive interrupt select logic dx dr expand logic drr1 receive buffer rx fifo interrupt drr2 receive buffer rx fifo registers rbr1 register rbr2 register mcbsp registers and control logic clkx fsx clkr fsr 16 compand logic dxr2 transmit buffer rsr1 xsr2 xsr1 peripheral read bus 16 16 16 16 16 rsr2 dxr1 transmit buffer 16 lspclk mrint to cpu mcbsp rx interrupt logic rx fifo _15 ? rx fifo _1 rx fifo _0 rx fifo _15 ? rx fifo _1 rx fifo _0 mcbsp transmit interrupt select logic tx fifo interrupt tx fifo registers mxint to cpu tx interrupt logic 16 16 16 tx fifo _15 ? tx fifo _1 tx fifo _0 tx fifo _15 ? tx fifo _1 tx fifo _0 peripheral write bus figure 4?9. mcbsp module with fifo peripherals 75 april 2001 ? revised december 2004 sprs174l table 4?7 provides a summary of the mcbsp registers. table 4?7. mcbsp register summary name address 0x00 78xxh type (r/w) reset value (hex) description data registers, receive, transmit ? ? ? ? 0x0000 mcbsp receive buffer register ? ? ? 0x0000 mcbsp receive shift register ? ? ? 0x0000 mcbsp transmit shift register drr2 00 r 0x0000 mcbsp data receive register 2 ? read first if the word size is greater than 16 bits, else ignore drr2 drr1 01 r 0x0000 mcbsp data receive register 1 ? read second if the word size is greater than 16 bits, else read drr1 only dxr2 02 w 0x0000 mcbsp data transmit register 2 ? write first if the word size is greater than 16 bits, else ignore dxr2 dxr1 03 w 0x0000 mcbsp data transmit register 1 ? write second if the word size is greater than 16 bits, else write to dxr1 only mcbsp control registers spcr2 04 r/w 0x0000 mcbsp serial port control register 2 spcr1 05 r/w 0x0000 mcbsp serial port control register 1 rcr2 06 r/w 0x0000 mcbsp receive control register 2 rcr1 07 r/w 0x0000 mcbsp receive control register 1 xcr2 08 r/w 0x0000 mcbsp transmit control register 2 xcr1 09 r/w 0x0000 mcbsp transmit control register 1 srgr2 0a r/w 0x0000 mcbsp sample rate generator register 2 srgr1 0b r/w 0x0000 mcbsp sample rate generator register 1 multichannel control registers mcr2 0c r/w 0x0000 mcbsp multichannel register 2 mcr1 0d r/w 0x0000 mcbsp multichannel register 1 rcera 0e r/w 0x0000 mcbsp receive channel enable register partition a rcerb 0f r/w 0x0000 mcbsp receive channel enable register partition b xcera 10 r/w 0x0000 mcbsp transmit channel enable register partition a xcerb 11 r/w 0x0000 mcbsp transmit channel enable register partition b pcr 12 r/w 0x0000 mcbsp pin control register rcerc 13 r/w 0x0000 mcbsp receive channel enable register partition c rcerd 14 r/w 0x0000 mcbsp receive channel enable register partition d xcerc 15 r/w 0x0000 mcbsp transmit channel enable register partition c xcerd 16 r/w 0x0000 mcbsp transmit channel enable register partition d ? drr2/drr1 and dxr2/dxr1 share the same addresses of receive and transmit fifo registers in fifo mode. ? fifo pointers advancing is based on order of access to drr2/drr1 and dxr2/dxr1 registers. peripherals 76 april 2001 ? revised december 2004 sprs174l table 4?7. mcbsp register summary (continued) name address 0x00 78xxh type (r/w) reset value (hex) description multichannel control registers (continued) rcere 17 r/w 0x0000 mcbsp receive channel enable register partition e rcerf 18 r/w 0x0000 mcbsp receive channel enable register partition f xcere 19 r/w 0x0000 mcbsp transmit channel enable register partition e xcerf 1a r/w 0x0000 mcbsp transmit channel enable register partition f rcerg 1b r/w 0x0000 mcbsp receive channel enable register partition g rcerh 1c r/w 0x0000 mcbsp receive channel enable register partition h xcerg 1d r/w 0x0000 mcbsp transmit channel enable register partition g xcerh 1e r/w 0x0000 mcbsp transmit channel enable register partition h fifo mode registers (applicable only in fifo mode) fifo data registers ? drr2 00 r 0x0000 mcbsp data receive register 2 ? top of receive fifo ? read first fifo pointers will not advance drr1 01 r 0x0000 mcbsp data receive register 1 ? top of receive fifo ? read second for fifo pointers to advance dxr2 02 w 0x0000 mcbsp data transmit register 2 ? top of transmit fifo ? write first fifo pointers will not advance dxr1 03 w 0x0000 mcbsp data transmit register 1 ? top of transmit fifo ? write second for fifo pointers to advance fifo control registers mfftx 20 r/w 0xa000 mcbsp transmit fifo register mffrx 21 r/w 0x201f mcbsp receive fifo register mffct 22 r/w 0x0000 mcbsp fifo control register mffint 23 r/w 0x0000 mcbsp fifo interrupt register mffst 24 r/w 0x0000 mcbsp fifo status register ? drr2/drr1 and dxr2/dxr1 share the same addresses of receive and transmit fifo registers in fifo mode. ? fifo pointers advancing is based on order of access to drr2/drr1 and dxr2/dxr1 registers. peripherals 77 april 2001 ? revised december 2004 sprs174l 4.6 serial communications interface (sci) module the f281x and c281x devices include two serial communications interface (sci) modules. the sci modules support digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. the sci receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. both can be operated independently or simultaneously in the full-duplex mode. to ensure data integrity, the sci checks received data for break detection, parity, overrun, and framing errors. the bit rate is programmable to over 65 000 different speeds through a 16-bit baud-select register. features of each sci module include: ? two external pins: ? scitxd: sci transmit-output pin ? scirxd: sci receive-input pin note: both pins can be used as gpio if not used for sci. ? baud rate programmable to 64k different rates ? ? baud rate = lspclk (brr 1) * 8 , when brr 0 = lspclk 16 , when brr = 0 ? data-word format ? one start bit ? data-word length programmable from one to eight bits ? optional even/odd/no parity bit ? one or two stop bits ? four error-detection flags: parity, overrun, framing, and break detection ? two wake-up multiprocessor modes: idle-line and address bit ? half- or full-duplex operation ? double-buffered receive and transmit functions ? transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. ? transmitter: txrdy flag (transmitter-buffer register is ready to receive another character) and tx empty flag (transmitter-shift register is empty) ? receiver: rxrdy flag (receiver-buffer register is ready to receive another character), brkdt flag (break condition occurred), and rx error flag (monitoring four interrupt conditions) ? separate enable bits for transmitter and receiver interrupts (except brkdt) ? max bit rate 150 mhz 2 8 9.375 10 6 b s ? serial port performance is limited by i/o buffer switching speed. internal prescalers must be adjusted such that the peripheral speed is less than the i/o buffer speed limit?20 mhz maximum. peripherals 78 april 2001 ? revised december 2004 sprs174l ? nrz (non-return-to-zero) format ? ten sci module control registers located in the control register frame beginning at address 7050h note: all registers in this module are 8-bit registers that are connected to peripheral frame 2. when a register is accessed, the register data is in the lower byte (7 ?0), and the upper byte (15 ?8) is read as zeros. writing to the upper byte has no effect. enhanced features: ? auto baud-detect hardware logic ? 16-level transmit/receive fifo the sci port operation is configured and controlled by the registers listed in table 4?8 and table 4?9. table 4?8. sci-a registers ? name address size (x16) description sciccra 0x00 7050 1 sci-a communications control register scictl1a 0x00 7051 1 sci-a control register 1 scihbauda 0x00 7052 1 sci-a baud register, high bits scilbauda 0x00 7053 1 sci-a baud register, low bits scictl2a 0x00 7054 1 sci-a control register 2 scirxsta 0x00 7055 1 sci-a receive status register scirxemua 0x00 7056 1 sci-a receive emulation data buffer register scirxbufa 0x00 7057 1 sci-a receive data buffer register scitxbufa 0x00 7059 1 sci-a transmit data buffer register scifftxa 0x00 705a 1 sci-a fifo transmit register sciffrxa 0x00 705b 1 sci-a fifo receive register sciffcta 0x00 705c 1 sci-a fifo control register scipria 0x00 705f 1 sci-a priority control register ? shaded registers are new registers for the fifo mode. table 4?9. sci-b registers ?? name address size (x16) description sciccrb 0x00 7750 1 sci-b communications control register scictl1b 0x00 7751 1 sci-b control register 1 scihbaudb 0x00 7752 1 sci-b baud register, high bits scilbaudb 0x00 7753 1 sci-b baud register, low bits scictl2b 0x00 7754 1 sci-b control register 2 scirxstb 0x00 7755 1 sci-b receive status register scirxemub 0x00 7756 1 sci-b receive emulation data buffer register scirxbufb 0x00 7757 1 sci-b receive data buffer register scitxbufb 0x00 7759 1 sci-b transmit data buffer register scifftxb 0x00 775a 1 sci-b fifo transmit register sciffrxb 0x00 775b 1 sci-b fifo receive register sciffctb 0x00 775c 1 sci-b fifo control register sciprib 0x00 775f 1 sci-b priority control register ? shaded registers are new registers for the fifo mode. ? registers in this table are mapped to peripheral bus 16 space. this space only allows 16-bit accesses. 32-bit accesses produce undefined res ults. peripherals 79 april 2001 ? revised december 2004 sprs174l figure 4?10 shows the sci module block diagram. tx fifo _0 lspclk wut frame format and mode even/odd enable parity sci rx interrupt select logic brkdt rxrdy scirxst.6 scictl1.3 8 scictl2.1 rx/bk int ena scirxd scirxst.1 txena sci tx interrupt select logic tx empty txrdy scictl2.0 tx int ena scitxd rxena scirxd rxwake scictl1.6 rx err int ena txwake scitxd sciccr.6 sciccr.5 scitxbuf.7?0 scihbaud. 15 ? 8 baud rate msbyte register scilbaud. 7 ? 0 transmitter?data buffer register 8 scictl2.6 scictl2.7 baud rate lsbyte register rxshf register txshf register scirxst.5 1 tx fifo _1 ????? tx fifo _15 8 tx fifo registers tx fifo tx interrupt logic txint scifftx.14 rx fifo _15 scirxbuf.7?0 receive data buffer register scirxbuf.7?0 ????? rx fifo_1 rx fifo _0 8 rx fifo registers scictl1.0 rx interrupt logic rxint rx fifo sciffrx.15 rxffovf rx error scirxst.7 pe fe oe rx error scirxst.4 ? 2 to cpu to cpu autobaud detect logic scictl1.1 sciffena interrupts interrupts figure 4?10. serial communications interface (sci) module block diagram peripherals 80 april 2001 ? revised december 2004 sprs174l 4.7 serial peripheral interface (spi) module the f281x and c281x devices include the four-pin serial peripheral interface (spi) module. the spi is a high-speed, synchronous serial i/o port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. normally, the spi is used for communications between the dsp controller and external peripherals or another processor. typical applications include external i/o or peripheral expansion through devices such as shift registers, display drivers, and adcs. multidevice communications are supported by the master/slave operation of the spi. the spi module features include: ? four external pins: ? spisomi: spi slave-output/master-input pin ? spisimo: spi slave-input/master-output pin ? spiste : spi slave transmit-enable pin ? spiclk: spi serial-clock pin note: all four pins can be used as gpio, if the spi module is not used. ? two operational modes: master and slave ? baud rate: 125 different programmable rates ? baud rate = lspclk (spibrr 1) , when brr 0 = lspclk 4 , when brr = 0, 1, 2, 3 serial port performance is limited by i/o buffer switching speed. internal prescalers must be adjusted such that the peripheral speed is less than the i/o buffer speed limit?20 mhz maximum. ? data word length: one to sixteen data bits ? four clocking schemes (controlled by clock polarity and clock phase bits) include: ? falling edge without phase delay: spiclk active-high. spi transmits data on the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. ? falling edge with phase delay: spiclk active-high. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge without phase delay: spiclk inactive-low. spi transmits data on the rising edge of the spiclk signal and receives data on the falling edge of the spiclk signal. ? rising edge with phase delay: spiclk inactive-low. spi transmits data one half-cycle ahead of the falling edge of the spiclk signal and receives data on the rising edge of the spiclk signal. ? simultaneous receive and transmit operation (transmit function can be disabled in software) ? transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. ? nine spi module control registers: located in control register frame beginning at address 7040h. note: all registers in this module are 16-bit registers that are connected to peripheral frame 2. when a register is accessed, the register data is in the lower byte (7 ?0), and the upper byte (15 ?8) is read as zeros. writing to the upper byte has no effect. enhanced feature: ? 16-level transmit/receive fifo ? delayed transmit control peripherals 81 april 2001 ? revised december 2004 sprs174l the spi port operation is configured and controlled by the registers listed in table 4?10. table 4?10. spi registers name address size (x16) description spiccr 0x00 7040 1 spi configuration control register spictl 0x00 7041 1 spi operation control register spists 0x00 7042 1 spi status register spibrr 0x00 7044 1 spi baud rate register spirxemu 0x00 7046 1 spi receive emulation buffer register spirxbuf 0x00 7047 1 spi serial input buffer register spitxbuf 0x00 7048 1 spi serial output buffer register spidat 0x00 7049 1 spi serial data register spifftx 0x00 704a 1 spi fifo transmit register spiffrx 0x00 704b 1 spi fifo receive register spiffct 0x00 704c 1 spi fifo control register spipri 0x00 704f 1 spi priority control register note: the above registers are mapped to peripheral frame 2. this space only allows 16-bit accesses. 32-bit accesses produce unde fined results. peripherals 82 april 2001 ? revised december 2004 sprs174l figure 4?11 is a block diagram of the spi in slave mode. s spictl.0 spi int flag spi int ena spists.6 s clock polarity talk lspclk 4 5 61 2 30 0 1 2 3 spi bit rate state control spirxbuf buffer register clock phase receiver overrun flag spictl.4 overrun int ena spiccr.3 ? 0 spibrr.6 ? 0 spiccr.6 spictl.3 spidat.15 ? 0 spictl.1 m s m master/slave spists.7 spidat data register m s spictl.2 spi char spisimo spisomi spiclk sw2 s m m s sw3 to cpu m sw1 spitxbuf buffer register rx fifo _0 rx fifo _1 ????? rx fifo _15 tx fifo registers tx fifo _0 tx fifo _1 ????? tx fifo _15 rx fifo registers 16 16 16 tx interrupt logic rx interrupt logic spiint/spirxint spitxint spiffovf flag spiffrx.15 16 tx fifo interrupt rx fifo interrupt spirxbuf spitxbuf spifftx.14 spiffena spiste ? ? spiste is driven low by the master for a slave device. figure 4?11. serial peripheral interface module block diagram (slave mode) peripherals 83 april 2001 ? revised december 2004 sprs174l 4.8 gpio mux the gpio mux registers, are used to select the operation of shared pins on the f281x and c281x devices. the pins can be individually selected to operate as ?digital i/o? or connected to ?peripheral i/o? signals (via the gpxmux registers). if selected for ?digital i/o? mode, registers are provided to configure the pin direction (via the gpxdir registers) and to qualify the input signal to remove unwanted noise (via the gpxqual) registers). table 4?11 lists the gpio mux registers. table 4?11. gpio mux registers ?? name address size (x16) register description gpamux 0x00 70c0 1 gpio a mux control register gpadir 0x00 70c1 1 gpio a direction control register gpaqual 0x00 70c2 1 gpio a input qualification control register reserved 0x00 70c3 1 gpbmux 0x00 70c4 1 gpio b mux control register gpbdir 0x00 70c5 1 gpio b direction control register gpbqual 0x00 70c6 1 gpio b input qualification control register reserved 0x00 70c7 1 reserved 0x00 70c8 1 reserved 0x00 70c9 1 reserved 0x00 70ca 1 reserved 0x00 70cb 1 gpdmux 0x00 70cc 1 gpio d mux control register gpddir 0x00 70cd 1 gpio d direction control register gpdqual 0x00 70ce 1 gpio d input qualification control register reserved 0x00 70cf 1 gpemux 0x00 70d0 1 gpio e mux control register gpedir 0x00 70d1 1 gpio e direction control register gpequal 0x00 70d2 1 gpio e input qualification control register reserved 0x00 70d3 1 gpfmux 0x00 70d4 1 gpio f mux control register gpfdir 0x00 70d5 1 gpio f direction control register reserved 0x00 70d6 1 reserved 0x00 70d7 1 gpgmux 0x00 70d8 1 gpio g mux control register gpgdir 0x00 70d9 1 gpio g direction control register reserved 0x00 70da 1 reserved 0x00 70db 1 reserved 0x00 70dc 0x00 70df 4 ? reserved locations will return undefined values and writes will be ignored. ? not all inputs will support input signal qualification. these registers are eallow protected. this prevents spurious writes from overwriting the contents and corrupting the system. peripherals 84 april 2001 ? revised december 2004 sprs174l if configured for ?digital i/o? mode, additional registers are provided for setting individual i/o signals (via the gpxset registers), for clearing individual i/o signals (via the gpxclear registers), for toggling individual i/o signals (via the gpxtoggle registers), or for reading/writing to the individual i/o signals (via the gpxdat registers). table 4?12 lists the gpio data registers. for more information, see the tms320x281x system control and interrupts reference guide (literature number spru078). table 4?12. gpio data registers ?? name address size (x16) register description gpadat 0x00 70e0 1 gpio a data register gpaset 0x00 70e1 1 gpio a set register gpaclear 0x00 70e2 1 gpio a clear register gpatoggle 0x00 70e3 1 gpio a toggle register gpbdat 0x00 70e4 1 gpio b data register gpbset 0x00 70e5 1 gpio b set register gpbclear 0x00 70e6 1 gpio b clear register gpbtoggle 0x00 70e7 1 gpio b toggle register reserved 0x00 70e8 1 reserved 0x00 70e9 1 reserved 0x00 70ea 1 reserved 0x00 70eb 1 gpddat 0x00 70ec 1 gpio d data register gpdset 0x00 70ed 1 gpio d set register gpdclear 0x00 70ee 1 gpio d clear register gpdtoggle 0x00 70ef 1 gpio d toggle register gpedat 0x00 70f0 1 gpio e data register gpeset 0x00 70f1 1 gpio e set register gpeclear 0x00 70f2 1 gpio e clear register gpetoggle 0x00 70f3 1 gpio e toggle register gpfdat 0x00 70f4 1 gpio f data register gpfset 0x00 70f5 1 gpio f set register gpfclear 0x00 70f6 1 gpio f clear register gpftoggle 0x00 70f7 1 gpio f toggle register gpgdat 0x00 70f8 1 gpio g data register gpgset 0x00 70f9 1 gpio g set register gpgclear 0x00 70fa 1 gpio g clear register gpgtoggle 0x00 70fb 1 gpio g toggle register reserved 0x00 70fc 0x00 70ff 4 ? reserved locations will return undefined values and writes will be ignored. ? these registers are not eallow protected. the above registers will typically be accessed regularly by the user. peripherals 85 april 2001 ? revised december 2004 sprs174l figure 4?12 shows how the various register bits select the various modes of operation for gpio function. peripheral i/o mux 01 mux 1 0 pin internal (pullup or pulldown) digital i/o xrs high-impedance enable (1) high- impedance control gpxdir register bit gpxmux register bit gpxqual register gpxdat/set/clear/toggle register bit(s) input qualification sysclkout notes: a. in the gpio mode, when the gpio pin is configured for output operation, reading the gpxdat data register only gives the value written, not the value at the pin. in the peripheral mode, the state of the pin can be read through the gpxdat register, provid ed the corresponding direction bit is zero (input mode). b. some selected input signals are qualified by the sysclkout. the gpxqual register specifies the qualification sampling period. the sampling window is 6 samples wide and the output is only changed when all samples are the same (all 0?s or all 1? s). this feature removes unwanted spikes from the input signal. figure 4?12. gpio/peripheral pin multiplexing note: the input function of the gpio pin and the input path to the peripheral are always enabled. it is the output function of the gpio pin that is multiplexed with the output path of the primary (peripheral) function. since the output buffer of a pin connects back to the input buffer, any gpio signal present at the pin will be propagated to the peripheral module as well. therefore, when a pin is configured for gpio operation, the corresponding peripheral functionality (and interrupt-generating capability) must be disabled. otherwise, interrupts may be inadvertently triggered. this is especially critical when the pdpinta and pdpintb pins are used as gpio pins, since a value of zero for gpddat.0 or gpddat.5 (pdpintx ) will put pwm pins in a high-impedance state. the cxtrip and txctrip pins will also put the corresponding pwm pins in high impedance, if they are driven low (as gpio pins) and bit extconx.0 = 1. development support 86 april 2001 ? revised december 2004 sprs174l 5 development support texas instruments (ti) offers an extensive line of development tools for the c28x ? generation of dsps, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development of f281x- and c281x-based applications: software development tools ? code composer studio ? integrated development environment (ide) ? c/c++ compiler ? code generation tools ? assembler/linker ? cycle accurate simulator ? application algorithms ? sample applications code hardware development tools ? 2812 ezdsp ? jtag-based emulators ? spi515, xds510pp, xds510pp plus, xds510 usb ? universal 5-v dc power supply ? documentation and cables 5.1 device and development support tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all [tms320] dsp devices and support tools. each [tms320] dsp commercial family member has one of three prefixes: tmx, tmp, or tms (e.g., tms320f2812ghh). texas instruments recommends two of three possible prefix designators for its support tools: tmdx and tmds. these prefixes represent evolutionary stages of product development from engineering prototypes (tmx/ tmdx) through fully qualified production devices/tools (tms / tmds). tmx experimental device that is not necessarily representative of the final device? s electrical specifications tmp final silicon die that conforms to the device?s electrical specifications but has not completed quality and reliability verification tms fully qualified production device support tool development evolutionary flow: tmdx development-support product that has not yet completed texas instruments internal qualification testing. tmds fully qualified development-support product tmx and tmp devices and tmdx development-support tools are shipped against the following disclaimer: ?developmental product is intended for internal evaluation purposes.? tms devices and tmds development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti?s standard warranty applies. predictions show that prototype devices ( tmx or tmp) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. tms320 is a trademark of texas instruments. development support 87 april 2001 ? revised december 2004 sprs174l ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pbk) and temperature range (for example, a). figure 5?1 provides a legend for reading the complete device name for any tms320x28x family member. prefix tms 320 f 2810 pbk tmx = experimental device tmp = prototype device tms = qualified device device family 320 = tms320 ? dsp family technology package type ? ? ghh = 179-ball microstar bga ? zhh = 179-ball microstar bga (lead-free) pgf = 176-pin lqfp pbk = 128-pin lqfp f = flash eeprom (1.8-v/1.9-v core/3.3-v i/o) c = rom (1.8-v/1.9-v core/3.3-v i/o) device 2810 2811 2812 ? bga = ball grid array lqfp = low-profile quad flatpack ? lqfp package not yet available lead (pb)-free. for estimated conversion dates, go to www.ti.com/leadfree temperature range a = ?40 c to 85 c s = ?40 c to 125 c q = ?40 c to 125 c ? q100 fault grading a figure 5?1. tms320x28x device nomenclature 5.2 documentation support extensive documentation supports all of the tms320 ? dsp family generations of devices from product announcement through applications development. the types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. useful reference documentation includes: tms320c28x dsp cpu and instruction set reference guide (literature number spru430) describes the central processing unit (cpu) and the assembly language instructions of the tms320c28x ? fixed-point digital signal processors (dsps). it also describes emulation features available on these dsps. tms320x281x analog-to-digital converter (adc) reference guide (literature number spru060) describes the adc module. the module is a 12-bit pipelined adc. the analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (muxs), sample-and-hold (s/h) circuits, the conversion core, voltage regulators, and other analog supporting circuits. digital circuits, referred to as the wrapper in this document, include programmable conversion sequencer, result registers, interface to analog circuits, interface to device peripheral bus, and interface to other on-chip modules. tms320x281x boot rom reference guide (literature number spru095) describes the purpose and features of the bootloader (factory-programmed boot-loading software). it also describes other contents of the device on-chip boot rom and identifies where all of the information is located within that memory. tms320x281x event manager (ev) reference guide (literature number spru065) describes the ev modules that provide a broad range of functions and features that are particularly useful in motion control and motor control applications. the ev modules include general-purpose (gp) timers, full-compare/pwm units, capture units, and quadrature-encoder pulse (qep) circuits. tms320x281x external interface (xintf) reference guide (literature number spru067) describes the external interface (xintf) of the 281x digital signal processors (dsps). development support 88 april 2001 ? revised december 2004 sprs174l tms320x281x multi-channel buffered serial ports (mcbsps) reference guide (literature number spru061) describes the mcbsp) available on the 281x devices. the mcbsps allow direct interface between a dsp and other devices in a system. tms320x281x system control and interrupts reference guide (literature number spru078) describes the various interrupts and system control features of the 281x digital signal processors (dsps). tms320x281x, 280x enhanced controller area network (ecan) reference guide (literature number spru074) describes the ecan that uses established protocol to communicate serially with other controllers in electrically noisy environments. with 32 fully configurable mailboxes and time-stamping feature, the ecan module provides a versatile and robust serial communication interface. the ecan module implemented in the c28x dsp is compatible with the can 2.0b standard (active). tms320x281x, 280x peripheral reference guide (literature number spru566) describes the peripheral reference guides of the 28x digital signal processors (dsps). tms320x281x, 280x serial communication interface (sci) reference guide (literature number spru051) describes the sci that is a two-wire asynchronous serial port, commonly known as a uart. the sci modules support digital communications between the cpu and other asynchronous peripherals that use the standard non-return-to-zero (nrz) format. tms320x281x, 280x serial peripheral interface (spi) reference guide (literature number spru059) describes the spi ? a high-speed synchronous serial input/output (i/o) port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. the spi is used for communications between the dsp controller and external peripherals or another controller. 3.3 v dsp for digital motor control application report (literature number spra550). new generations of motor control digital signal processors (dsps) lower their supply voltages from 5 v to 3.3 v to offer higher performance at lower cost. replacing traditional 5-v digital control circuitry by 3.3-v designs introduce no additional system cost and no significant complication in interfacing with ttl and cmos compatible components, as well as with mixed voltage ics such as power transistor gate drivers. just like 5-v based designs, good engineering practice should be exercised to minimize noise and emi effects by proper component layout and pcb design when 3.3-v dsp, adc, and digital circuitry are used in a mixed signal environment, with high and low voltage analog and switching signals, such as a motor control system. in addition, software techniques such as random pwm method can be used by special features of the texas instruments (ti) tms320x24xx dsp controllers to significantly reduce noise effects caused by emi radiation. this application report reviews designs of 3.3-v dsp versus 5-v dsp for low hp motor control applications. the application report first describes a scenario of a 3.3-v-only motor controller indicating that for most applications, no significant issue of interfacing between 3.3 v and 5 v exists. cost-effective 3.3-v ? 5-v interfacing techniques are then discussed for the situations where such interfacing is needed. on-chip 3.3-v adc versus 5-v adc is also discussed. sensitivity and noise effects in 3.3-v and 5-v adc conversions are addressed. guidelines for component layout and printed circuit board (pcb) design that can reduce system?s noise and emi effects are summarized in the last section. the tms320c28x instruction set simulator technical overview (literature number spru608) describes the simulator, available within the code composer studio for tms320c2000 ide, that simulates the instruction set of the c28x core. tms320c28x dsp/bios application programming interface (api) reference guide (literature number spru625) describes development using dsp/bios. tms320c28x assembly language tools user?s guide (literature number spru513) describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the tms320c28x ? device. development support 89 april 2001 ? revised december 2004 sprs174l tms320c28x optimizing c compiler user?s guide (literature number spru514) describes the tms320c28x ? c/c++ compiler. this compiler accepts ansi standard c/c++ source code and produces tms320 ? dsp assembly language source code for the tms320c28x device. programming examples for the tms320f281x ecan (literature number spra876) contains several programming examples to illustrate how the ecan module is set up for different modes of operation. the objective is to help you come up to speed quickly in programming the ecan. all programs have been extensively commented to aid easy understanding. the canaly zer tool from vector cantech, inc. was used to monitor and control the bus operation. all projects and canalyzer configuration files are included in the attached spra876.zip file. tms320f2810, tms320f2811, tms320f2812 adc calibration (literature number spra989) describes a method for improving the absolute accuracy of the 12-bit analog-to-digital converter (adc) found on the f2810/f2811/f2812 devices. due to inherent gain and offset errors, the absolute accuracy of the adc is impacted. the methods described in this application note can improve the absolute accuracy of the adc to achieve levels better than 0.5%. this application note is accompanied by an example program (adccalibration.zip) that executes from ram on the f2812 ezdsp. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 ? dsp newsletter, details on signal processing , is published quarterly and distributed to update tms320 ? dsp customers on product information. updated information on the tms320 ? dsp controllers can be found on the worldwide web at: http://www.ti.com . to send comments regarding this tms320f281x/tms320c281x data manual (literature number sprs174), use the comments@books.sc.ti.com email address, which is a repository for feedback. for questions and support, contact the product information center listed at the http://www.ti.com/sc/docs/pic/home.htm site. electrical specifications 90 april 2001 ? revised december 2004 sprs174l 6 electrical specifications this section provides the absolute maximum ratings and the recommended operating conditions for the tms320f281x and tms320c281x dsps. 6.1 absolute maximum ratings unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under section 6.2 is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to v ss . supply voltage range, v ddio , v dda1 , v dda2 , v ddaio , and av ddrefbg ? 0.3 v to 4.6 v . . . . . . . . . . . . . supply voltage range, v dd , v dd1 ? 0.5 v to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dd3vfl range ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v in ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.3 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v in < 0 or v in > v ddio ) ? 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v ddio ) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating ambient temperature ranges, t a : a version (ghh, pgf, pbk) ? ? 40 c to 85 c . . . . . . . . . . . . . . t a : s version (ghh, pgf, pbk) ? ? 40 c to 125 c . . . . . . . . . . . . t a : q version (ghh, pgf, pbk) ? ? 40 c to 125 c . . . . . . . . . . . . . storage temperature range, t stg ? ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? continuous clamp current per pin is 2 ma ? long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall d evice life. for additional information, see ic package thermal metrics application report (literature number spra953) and reliability data for tms320lf24x and tms320f281x devices application repor t (literature number spra963). replaced by q temperature option from silicon revision e onwards electrical specifications 91 april 2001 ? revised december 2004 sprs174l 6.2 recommended operating conditions ? min nom max unit v ddio device supply voltage, i/o 3.14 3.3 3.47 v v dd , v dd1 device supply voltage, cpu 1.8 v (135 mhz) 1.71 1.8 1.89 v v dd , v dd1 device supply voltage, cpu 1.9 v (150 mhz) 1.81 1.9 2 v v ss supply ground 0 v v dda1 , v dda2 , av ddrefbg , v ddaio adc supply voltage 3.14 3.3 3.47 v v dd3vfl flash programming supply voltage 3.14 3.3 3.47 v f sysclkout device clock frequency v dd = 1.9 v 5% 2 150 mhz f sysclkout device clock frequency (system clock) v dd = 1.8 v 5% 2 135 mhz all inputs except xclkin 2 v ddio v ih high-level input voltage all inputs except xclkin 2 v ddio v v ih high-level input voltage xclkin (@ 50 a max) 0.7v dd v dd v v il low-level input voltage all inputs except xclkin 0.8 v v il low-level input voltage xclkin (@ 50 a max) 0.3v dd v i oh high-level output source current, all i/os except group 2 ? 4 ma i oh high-level output source current, v oh = 2.4 v group 2 ? ? 8 ma i ol low-level output sink current, all i/os except group 2 4 ma i ol low-level output sink current, v ol = v ol max group 2 ? 8 ma ambient a version ? 40 85 c t a ambient temperature s version ? 40 125 c t a temperature q version ? 40 125 c ? see section 6.8 for power sequencing of v ddio , v ddaio , v dd , v dda1 /v dda2 /av ddrefbg , and v dd3vfl . ? group 2 pins are as follows: xintf pins, t1ctrip_pdpinta , tdo, xclkout, xf, emu0, and emu1. replaced by q temperature option from silicon revision e onwards electrical specifications 92 april 2001 ? revised december 2004 sprs174l 6.3 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = i oh max 2.4 v v oh high-level output voltage i oh = 50 a v ddio ? 0.2 v v ol low-level output voltage i ol = i ol max 0.4 v v ol low-level output voltage i ol = i ol max 0.4 v input with pullup v ddio = 3.3 v, v in = 0 v ?80 ?140 ?190 i il ? input current with pullup v ddio = 3.3 v, v in = 0 v ?80 ?14 0 ?19 0 a i il ? current (low level) with pulldown v ddio = 3.3 v, v in = 0 v 2 a i il ? input current with pullup v ddio = 3.3 v, v in = 0 v all i/os (including xrs ) except evb ?80 ?140 ?190 a i il ? input current (low level) with pullup ddio v in = 0 v gpiob/evb ?13 ?25 ?35 a (low level) with pulldown v ddio = 3.3 v, v in = 0 v 2 input current with pullup v ddio = 3.3 v, v in = v dd 2 i ih input current (high level) with pulldown ? v ddio = 3.3 v, 28 50 80 a i ih current (high level ) with pulldown ? v ddio = 3.3 v, v in = v dd 28 50 80 a i oz output current, high-impedance state (off-state) v o = v ddio or 0 v 2 a c i input capacitance 2 pf c o output capacitance 3 pf ? applicable to c281x devices ? applicable to f281x devices the following pins have no internal pu/pd: gpioe0, gpioe1, gpiof0, gpiof1, gpiof2, gpiof3, gpiof12, gpiog4, and gpiog5. ? the following pins have an internal pulldown: xmp/mc , testsel, and trst . 6.4 current consumption by power-supply pins over recommended operating conditions during low-power modes at 150-mhz sysclkout (tms320f281x) mode test conditions i dd i ddio i dd3vfl i dda ? mode test conditions typ max ? typ max ? typ max ? typ max ? operational all peripheral clocks are enabled. all pwm pins are toggled at 100 khz. data is continuously transmitted out of the scia, scib, and can ports. the hardware multiplier is exercised. code is running out of flash with 5 wait-states. 195 ma 230 ma 15 ma 30 ma 40 ma 45 ma 40 ma 50 ma idle ? flash is powered down ? xclkout is turned off ? all peripheral clocks are on, except adc 125 ma 150 ma 5 ma 10 ma 2 a 4 a 1 a 20 a standby ? flash is powered down ? peripheral clocks are turned off ? pins without an internal pu/pd are tied high/low 5 ma 10 ma 5 a 20 a 2 a 4 a 1 a 20 a halt ? flash is powered down ? peripheral clocks are turned off ? pins without an internal pu/pd are tied high/low ? input clock is disabled 70 a 5 a 20 a 2 a 4 a 1 a 20 a ? i dda includes current into v dda1 , v dda2 , v dd1 , av ddrefbg , and v ddaio pins. ? max numbers are at 125 c, and max voltage (v dd = 2.0 v; v ddio , v dd3vfl , v dda = 3.6 v). electrical specifications 93 april 2001 ? revised december 2004 sprs174l note: halt and standby modes cannot be used when the pll is disabled. 6.5 current consumption by power-supply pins over recommended operating conditions during low-power modes at 150-mhz sysclkout (tms320c281x) mode test conditions i dd i ddio i dda ? mode test conditions typ max ? typ max ? typ max ? operational all peripheral clocks are enabled. all pwm pins are toggled at 100 khz. data is continuously transmitted out of the scia, scib, and can ports. the hardware multiplier is exercised. code is running out of rom with 5 wait-states. 210 ma 260 ma 20 ma 30ma 40 ma 50 ma idle ? xclkout is turned off ? all peripheral clocks are on, except adc 140 ma 155 ma 20 ma 30 ma 5 a 10 a standby ? peripheral clocks are turned off ? pins without an internal pu/pd are tied high/low 5 ma 10ma 1 ma 3 ma 5 a 10 a halt ? peripheral clocks are turned off ? pins without an internal pu/pd are tied high/low ? input clock is disabled 70 a 5 a 10 a 1 a ? i dda includes current into v dda1 , v dda2 , v dd1 , av ddrefbg , and v ddaio pins. electrical specifications 94 april 2001 ? revised december 2004 sprs174l 6.6 current consumption graphs 0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 sysclkout (mhz) idd iddio idd3vfl idda total 3.3?v current current (ma) notes: a. test conditions are as defined in table 6?5 for operational currents. b. i dd represents the total current drawn from the 1.8-v rail (v dd ). it includes a trivial amount of current (<1 ma) drawn by v dd1 . c. idda represents the current drawn by vdda1 and vdda2 rails. d. total 3.3-v current is the sum of i ddio , i dd3vfl , and i dda . it includes a trivial amount of current (<1 ma) drawn by vddaio. . figure 6?1. f2812/f2811/f2810 typical current consumption over frequency 0 100 200 300 400 500 600 700 0 20 40 60 80 100 120 140 160 sysclkout (mhz) total power power (mw) figure 6?2. f2812/f2811/f2810 typical power consumption over frequency electrical specifications 95 april 2001 ? revised december 2004 sprs174l 0 50 100 150 200 250 0 20 40 60 80 100 120 140 160 sysclkout (mhz) idd iddio idda total 3.3?v current current (ma) notes: a. test conditions are as defined in table 6?5 for operational currents. b. i dd represents the total current drawn from the 1.8-v rail (v dd ). it includes a trivial amount of current (<1 ma) drawn by v dd1 . c. idda represents the current drawn by vdda1 and vdda2 rails. d. total 3.3-v current is the sum of i ddio and i dda . it includes a trivial amount of current (<1 ma) drawn by vddaio. figure 6?3. c2812/c2811/c2810 typical current consumption over frequency 0 100 200 300 400 500 600 0 20 40 60 80 100 120 140 160 total power sysclkout (mhz) power (mw) figure 6?4. c2812/c2811/c2810 typical power consumption over frequency electrical specifications 96 april 2001 ? revised december 2004 sprs174l 6.7 reducing current consumption 28x dsps incorporate a unique method to reduce the device current consumption. a reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. t able 6?1 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. table 6?1. typical current consumption by various peripherals (at 150 mhz) ? peripheral module i dd current reduction (ma) ecan 12 eva 6 evb 6 adc 8 ? sci 4 spi 5 mcbsp 13 ? all peripheral clocks are disabled upon reset. writing to/reading from peripheral registers is possible only after the peripher al clocks are turned on . ? this number represents the current drawn by the digital portion of the adc module. turning off the clock to the adc module resu lts in the elimination of the current drawn by the analog portion of the adc (i cca ) as well. 6.8 power sequencing requirements tms320f2812/f2811/f2810 silicon requires dual voltages (1.8-v or 1.9-v and 3.3-v) to power up the cpu, flash, rom, adc, and the i/os. to ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. the current f2812 silicon reference schematics (spectrum digital incorporated ezdsp. board) suggests two options for the power sequencing circuit. power sequencing is not needed for c281x devices. in other words, 3.3-v and 1.8-v (or 1.9-v) can ramp together. c281x can also be used on boards that have f281x power sequencing implemented; however, if the 1.8-v (or 1.9-v) rail lags the 3.3-v rail, the gpio pins are undefined until the 1.8-v rail reaches at least 1 v. ? option 1: in this approach, an external power sequencing circuit enables v ddio first, then v dd and v dd1 (1.8 v or 1.9 v). after 1.8 v (or 1.9 v) ramps, the 3.3 v for flash (v dd3vfl ) and adc (v dda1 /v dda2 /av ddrefbg ) modules are ramped up. while option 1 is still valid, ti has simplified the requirement. option 2 is the recommended approach. ? option 2: enable power to all 3.3-v supply pins (v ddio , v dd3vfl , v dda1 /v dda2 /v ddaio /av ddrefbg ) and then ramp 1.8 v (or 1.9 v) (v dd /v dd1 ) supply pins. 1.8 v or 1.9 v (v dd /v dd1 ) should not reach 0.3 v until v ddio has reached 2.5 v. this ensures the reset signal from the i/o pin has propagated through the i/o buffer to provide power-on reset to all the modules inside the device. see figure 6?10 for power-on reset timing. ? power-down sequencing: during power-down, the device reset should be asserted low (8 s, minimum) before the v dd supply reaches 1.5 v. this will help to keep on-chip flash logic in reset prior to the v ddio /v dd power supplies ramping down. it is recommended that the device reset control from ?low-dropout (ldo)? regulators or ezdsp is a trademark of spectrum digital incorporated. electrical specifications 97 april 2001 ? revised december 2004 sprs174l voltage supervisors be used to meet this constraint. ldo regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. see www.spectrumdigital.com for f2812 ezdsp ? schematics and updates. table 6?2. recommended ?low-dropout regulators? supplier part number texas instruments tps767d301 note: the gpio pins are undefined until v dd = 1 v and v ddio = 2.5 v. v dd_3.3v ? 2.5 v (see note a) 3.3 v v dd_1.8v ? xrs 1.8 v (or 1.9 v) xrs > 8 s 1.5 v 3.3 v <10 ms >1 ms power-up sequence power-down sequence 1.8 v (or 1.9 v) ? v dd_3.3v ?v ddio , v dd3vfl , v ddaio , v dda1 , v dda2 , av ddrefbg ? v dd_1.8v ?v dd , v dd1 notes: a. 1.8-v (or 1.9 v) supply should ramp after the 3.3-v supply reaches at least 2.5 v. b. reset (xrs ) should remain low until supplies and clocks are stable. see figure 6?10, power-on reset in microcomputer mode (xmp/mc = 0), for minimum requirements. c. voltage supervisor or ldo reset control will trip reset (xrs ) first when the 3.3-v supply is of f regulation. t ypically, this occurs a few milliseconds before the 1.8-v (or 1.9 v) supply reaches 1.5 v. d. keeping reset low (xrs ) at least 8 s prior to the 1.8-v (or 1.9 v) supply reaching 1.5 v will keep the flash module in complete reset before the supplies ramp down. e. since the state of gpio pins is undefined until the 1.8-v (or 1.9 v) supply reaches at least 1 v, this supply should be rampe d as quickly as possible (after the 3.3-v supply reaches at least 2.5 v). f. other than the power supply pins, no pin should be driven before the 3.3-v rail has been fully powered up. see note b see note d see note c figure 6?5. f2812/f2811/f2810 typical power-up and power-down sequence ? option 2 electrical specifications 98 april 2001 ? revised december 2004 sprs174l 6.9 signal transition levels note that some of the signals use different reference voltages, see the recommended operating conditions table. output levels are driven to a minimum logic-high level of 2.4 v and to a maximum logic-low level of 0.4 v. figure 6?6 shows output levels. 0.4 v (v ol ) 20% 2.4 v (v oh ) 80% figure 6?6. output levels output transition times are specified as follows: ? for a high-to-low transition , the level at which the output is said to be no longer high is below 80% of the total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage range and lower. ? for a low-to-high transition , the level at which the output is said to be no longer low is 20% of the total voltage range and higher and the level at which the output is said to be high is 80% of the total voltage range and higher. figure 6?7 shows the input levels. 0.8 v (v il ) 10% 2.0 v (v ih ) 90% figure 6?7. input levels input transition times are specified as follows: ? for a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower. ? for a low-to-high transition on an input signal, the level at which the input is said to be no longer low is 10% of the total voltage range and higher and the level at which the input is said to be high is 90% of the total voltage range and higher. note: see the individual timing diagrams for levels used for testing timing parameters. electrical specifications 99 april 2001 ? revised december 2004 sprs174l 6.10 timing parameter symbology timing parameter symbols used are created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid f fall time x unknown, changing, or don?t care level h hold time z high impedance r rise time su setup time t transition time v valid time w pulse duration (width) 6.11 general notes on timing parameters all output signals from the 28x devices (including xclkout) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. the signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. for actual cycle examples, see the appropriate cycle description section of this document. 6.12 test load circuit this test load circuit is used to measure all switching characteristics provided in this document. transmission line 4.0 pf 1.85 pf z0 = 50 ? (see note) tester pin electronics data sheet timing reference point output under test note: the data sheet provides timing at the device pin. for output timing analysis, the tester pin electronics and its transmiss ion line effects must be taken into account. a transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line eff ect. the transmission line is intended as a load only. it is not necessary to add or subtract the transmission line delay (2 ns or l onger) from the data sheet timing. 42 ? 3.5 nh device pin (see note) input requirements in this data sheet are tested with an input slew rate of < 4 volts per nanosecond (4 v/ns) at the device pin . figure 6?8. 3.3-v test load circuit electrical specifications 100 april 2001 ? revised december 2004 sprs174l 6.13 device clock table this section provides the timing requirements and switching characteristics for the various clock options available on the f281x and c281x dsps. table 6?3 lists the cycle times of various clocks. table 6?3. tms320f281x and tms320c281x clock table and nomenclature min nom max unit on-chip oscillator clock t c(osc) , cycle time 28.6 50 ns on-chip oscillator clock frequency 20 35 mhz xclkin t c(ci) , cycle time 6.67 250 ns xclkin frequency 4 150 mhz sysclkout t c(sco) , cycle time 6.67 500 ns sysclkout frequency 2 150 mhz xclkout t c(xco) , cycle time 6.67 2000 ns xclkout frequency 0.5 150 mhz hspclk t c(hco) , cycle time 6.67 13.3 ? ns hspclk frequency 75 ? 150 mhz lspclk t c(lco) , cycle time 13.3 26.6 ? ns lspclk frequency 37.5 ? 75 mhz adc clock t c(adcclk) , cycle time ? 40 ns adc clock frequency 25 mhz spi clock t c(spc) , cycle time 50 ns spi clock frequency 20 mhz mcbsp t c(ckg) , cycle time 50 ns mcbsp frequency 20 mhz xtimclk t c(xtim) , cycle time 6.67 ns xtimclk frequency 150 mhz ? the maximum value for adcclk frequency is 25 mhz. for sysclkout values of 25 mhz or lower, adcclk has to be sysclkout/2 or lowe r. adcclk = sysclkout is not a valid mode for any value of sysclkout. ? this is the default reset value if sysclkout = 150 mhz. 6.14 clock requirements and characteristics 6.14.1 input clock requirements the clock provided at the xclkin pin generates the internal cpu clock cycle. table 6?4. input clock frequency parameter min typ max unit resonator 20 35 f x input clock frequency crystal 20 35 mhz f x input clock frequency xclkin 4 150 mhz f l limp mode clock frequency 2 mhz electrical specifications 101 april 2001 ? revised december 2004 sprs174l table 6?5. xclkin timing requirements ? pll bypassed or enabled no. min max unit c8 t c(ci) cycle time, xclkin 6.67 250 ns c9 t f(ci) fall time, xclkin up to 30 mhz 6 ns c9 t f(ci) fall time, xclkin 30 mhz to 150 mhz 2 ns c10 t r(ci) rise time, xclkin up to 30 mhz 6 ns c10 t r(ci) rise time, xclkin 30 mhz to 150 mhz 2 ns c11 t w(cil) pulse duration, x1/xclkin low as a percentage of t c(ci) 40 60 % c12 t w(cih) pulse duration, x1/xclkin high as a percentage of t c(ci) 40 60 % table 6?6. xclkin timing requirements ? pll disabled no. min max unit c8 t c(ci) cycle time, xclkin 6.67 250 ns c9 t f(ci) fall time, xclkin up to 30 mhz 6 ns c9 t f(ci) fall time, xclkin 30 mhz to 150 mhz 2 ns c10 t r(ci) rise time, xclkin up to 30 mhz 6 ns c10 t r(ci) rise time, xclkin 30 mhz to 150 mhz 2 ns c11 t w(cil) pulse duration, x1/xclkin low as a percentage of t c(ci) xclkin 120 mhz 40 60 % c11 t w(cil) pulse duration, x1/xclkin low as a percentage of t c(ci) 120 < xclkin 150 mhz 45 55 % c12 t w(cih) pulse duration, x1/xclkin high as a percentage of t c(ci) xclkin 120 mhz 40 60 % c12 t w(cih ) pulse duration, x1/xclkin high as a percentage of t c(ci) 120 < xclkin 150 mhz 45 55 % table 6?7. possible pll configuration modes pll mode remarks sysclkout pll disabled invoked by tying xplldis pin low upon reset. pll block is completely disabled. clock input to the cpu (clkin) is directly derived from the clock signal present at the x1/xclkin pin. xclkin pll bypassed default pll configuration upon power-up, if pll is not disabled. the pll itself is bypassed. however, the /2 module in the pll block divides the clock input at the x1/xclkin pin by two before feeding it to the cpu. xclkin/2 pll enabled achieved by writing a non-zero value ?n? into pllcr register. the /2 module in the pll block now divides the output of the pll by two before feeding it to the cpu. (xclkin * n) / 2 electrical specifications 102 april 2001 ? revised december 2004 sprs174l 6.14.2 output clock characteristics table 6?8. xclkout switching characteristics (pll bypassed or enabled) ?? no. parameter min typ max unit c1 t c(xco) cycle time, xclkout 6.67 ns c3 t f(xco) fall time, xclkout 2 ns c4 t r(xco) rise time, xclkout 2 ns c5 t w(xcol) pulse duration, xclkout low h?2 h+2 ns c6 t w(xcoh) pulse duration, xclkout high h?2 h+2 ns c7 t p pll lock time ? 131 072t c(ci) ns ? a load of 40 pf is assumed for these parameters. ? h = 0.5t c(xco) the pll must be used for maximum frequency operation. ? this parameter has changed from 4096 xclkin cycles in the earlier revisions of the silicon. c4 c3 xclkout (see note b) xclkin c5 c9 c10 c1 c8 c6 (see note a) notes: a. the relationship of xclkin to xclkout depends on the divide factor chosen. the waveform relationship shown in figure 6? 9 is intended to illustrate the timing parameters only and may differ based on configuration. b. xclkout configured to reflect sysclkout. figure 6?9. clock timing 6.15 reset timing table 6?9. reset (xrs ) timing requirements ? min nom max unit t w(rsl1) pulse duration, stable xclkin to xrs high 8t c(ci) cycles t w(rsl2) pulse duration, xrs low warm reset 8t c(ci) cycles t w(rsl2) pulse duration, xrs low wd-initiated reset 512t c(ci) cycles t w(wdrs) pulse duration, reset pulse generated by watchdog 512t c(ci) cycles t d(ex) delay time, address/data valid after xrs high 32t c(ci) cycles t oscst ? oscillator start-up time 1 10 ms t su(xplldis) setup time for xplldis pin 16t c(ci) cycles t h(xplldis) hold time for xplldis pin 16t c(ci) cycles t h(xmp/mc) hold time for xmp/mc pin 16t c(ci) cycles t h(boot-mode) hold time for boot-mode pins 2520t c(ci) cycles ? if external oscillator/clock source are used, reset time has to be low at least for 1 ms after v dd reaches 1.5 v. ? dependent on crystal/resonator and board design. the boot rom reads the password locations. therefore, this timing requirement includes the wakeup time for flash. see the tms320x281x boot rom reference guide (literature number spru095) and tms320x281x system control and interrupts reference guide (literature number spru078) for further information. electrical specifications 103 april 2001 ? revised december 2004 sprs174l t w(rsl1) t h(xplldis) t h(xmp/mc) t h(boot-mode) (see note d) v ddio , v dd3vfl v ddan ? , v ddaio (3.3 v) (see note b) xclkin 2.5 v 0.3 v x1 xrs xf/xplldis xmp/mc boot-mode pins v dd , v dd1 (1.8 v (or 1.9 v)) xclkout i/o pins user-code dependent user-code dependent user-code dependent boot-rom execution starts peripheral/gpio function based on boot code gpio pins as input xplldis sampling gpiof14 xclkin/8 (see note c) gpio pins as input (state depends on internal pu/pd) t oscst (don?t care) (don?t care) user-code dependent address/data/ control address/data valid. internal boot-rom code execution phase user-code execution phase notes: a. the state of the gpio pins is undefined (i.e., they could be input or output) until the 1.8-v (or 1.9-v) supply reaches at least 1 v and 3.3-v supply reaches 2.5 v. b. v ddan ? v dda1 /v dda2 and av ddrefbg c. upon power up, sysclkout is xclkin/2 if the pll is enabled. since both the xtimclk and clkmode bits in the xintcnf2 register come up with a reset state of 1, sysclkout is further divided by 4 before it appears at xclkout. this explains why xclkout = xclkin/8 during this phase. d. after reset, the boot rom code executes instructions for 1260 sysclkout cycles (sysclkout = xclkin/2) and then samples boot mode pins. based on the status of the boot mode pin, the boot code branches to destination memory or boot code function in rom. the boot mode pins should be held high/low for at least 2520 xclkin cycles from boot rom execution time for proper selection of boot modes. if boot rom code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current sysclkout speed. the sysclkout will be based on user environment and could be with or without pll enabled. t d(ex) see note t su(xplldis) figure 6?10. power-on reset in microcomputer mode (xmp/mc = 0) (see note a) electrical specifications 104 april 2001 ? revised december 2004 sprs174l t w(rsl) t h(xplldis) t h(xmp/mc) t oscst v ddio , v dd3vfl v ddan , v ddaio (3.3 v) xclkin x1 xrs xf/xplldis xmp/mc v dd , v dd1 (1.8 v (or 1.9 v)) i/o pins xplldis sampling address/data/ control xclkout (don?t care) (don?t care) gpiof14/xf (user-code dependent) xclkin/8 (see note a) (don?t care) input configuration (state depends on internal pu/pd) user-code dependent address/data/control valid execution begins from external boot address 0x3fffc0 user-code dependent 2.5 v 0.3 v t d(ex) notes: a. upon power up, sysclkout is xclkin/2 if the pll is enabled. since both the xtimclk and clkmode bits in the xintcnf2 register come up with a reset state of 1, sysclkout is further divided by 4 before it appears at xclkout. this explains why xclkout = xclkin/8 during this phase. b. the state of the gpio pins is undefined (i.e., they could be input or output) until the 1.8-v (or 1.9-v) supply reaches at le ast 1 v and 3.3-v supply reaches 2.5 v.. see note b t su(xplldis) figure 6?11. power-on reset in microprocessor mode (xmp/mc = 1) electrical specifications 105 april 2001 ? revised december 2004 sprs174l xclkin/8 (xclkin * 5) t h(xplldis) t h(xmp/mc) t h(boot-mode) ? t w(rsl2) xclkin x1 xrs xf/xplldis xmp/mc boot-mode pins xclkout i/o pins address/data/ control boot-rom execution starts user-code execution starts user-code dependent user-code dependent user-code execution phase (don?t care) (don?t care) (don?t care) (don?t care) user-code dependent user-code execution peripheral/gpio function user-code dependent gpio pins as input (state depends on internal pu/pd) gpio pins as input gpiof14/xf xplldis sampling gpiof14 peripheral/gpio function ? after reset, the boot rom code executes instructions for 1260 sysclkout cycles (sysclkout = xclkin/2) and then samples boot mode pins. based on the status of the boot mode pin, the boot code branches to destination memory or boot code function in rom. the boot mode pins should be held high/low for at least 2520 xclkin cycles from boot rom execution time for proper selection of boo t modes. if boot rom code executes after power-on conditions (in debugger environment), the boot code execution time is based on the cur rent sysclkout speed. the sysclkout will be based on user environment and could be with or without pll enabled. t d(ex) t su(xplldis) figure 6?12. warm reset in microcomputer mode electrical specifications 106 april 2001 ? revised december 2004 sprs174l x1/xclkin sysclkout write to pllcr xclkin*2 (current cpu frequency) xclkin/2 (cpu frequency while pll is stabilizing with the desired frequency. this period (pll lock-up time, t p ) is 131 072 xclkin cycles long.) xclkin*4 (changed cpu frequency) figure 6?13. effect of writing into pllcr register electrical specifications 107 april 2001 ? revised december 2004 sprs174l 6.16 low-power mode wakeup timing table 6?10. idle mode timing requirements test conditions min nom max unit t w(wake-int) pulse duration, external wake-up without input qualifier 2*t c(sco) cycles t w(wake-int ) pulse duration, external wake-up signal with input qualifier 1*t c(sco) + iqt ? cycles table 6?11. idle mode switching characteristics parameter test conditions min typ max unit delay time, external wake signal to program execution resume ? ? wake-up from flash ? flash module in active state without input qualifier 8 * t c(sco) cycles t d(wake-idle) ? wake-up from flash ? flash module in active state with input qualifier 8 * t c(sco) + iqt ? cycles t d(wake-idle ) ? wake-up from flash ? flash module in sleep state without input qualifier 1050*t c(sco) cycles ? wake-up from flash ? flash module in sleep state with input qualifier 1050 * t c(sco) + iqt ? cycles ? wake-up from saram without input qualifier 8 * t c(sco) cycles ? wake-up from saram with input qualifier 8 * t c(sco) + iqt ? cycles ? input qualification time (iqt) = [5 x qualprd x 2] * t c(sco) ? this is the time taken to begin execution of the instruction that immediately follows the idle instruction. execution of an isr (triggered by the wake-up) signal involves additional latency. wake int ? xclkout ? a0?a15 t d(wake?idle) ? xclkout = sysclkout ? wake int can be any enabled interrupt, wdint , xnmi, or xrs . t w(wake?int) figure 6?14. idle entry and exit timing table 6?12. standby mode timing requirements test conditions min nom max unit t w(wake-int) pulse duration, external without input qualifier 12 * t c(ci) cycles t w(wake-int ) pulse duration, external wake-up signal with input qualifier (2 + qualstdby) ? * t c(ci) cycles ? qualstdby is a 6-bit field in the lpmcr0 register. electrical specifications 108 april 2001 ? revised december 2004 sprs174l table 6?13. standby mode switching characteristics parameter test conditions min typ max unit t d(idle-xcoh) delay time, idle instruction executed to xclkout high 32 * t c(sco) 12 * t c(ci) cycles delay time, external wake signal to program execution resume ? ? wake-up from flash ? flash module in active state without input qualifier 12 * t c(ci) cycles t d(wake-stby) ? wake-up from flash ? flash module in active state with input qualifier 12 * t c(ci) + t w(wake-int) cycles t d(wake-stby) ? wake-up from flash ? flash module in sleep state without input qualifier 1125 * t c(sco) cycles ? wake-up from flash ? flash module in sleep state with input qualifier 1125 * t c(sco) + t w(wake-int) cycles ? wake-up from saram without input qualifier 12 * t c(ci) cycles ? wake-up from saram with input qualifier 12 * t c(ci) + t w(wake-int) cycles ? this is the time taken to begin execution of the instruction that immediately follows the idle instruction. execution of an isr (triggered by the wake-up) signal involves additional latency. t w(wake-int) t d(wake-stby) t d(idle?xcoh) 32 sysclkout cycles wake-up signal x1/xclkin xclkout ? standby normal execution standby flushing pipeline a b c d e f device status notes: a. idle instruction is executed to put the device into standby mode. b. the pll block responds to the st andby signal. sysclkout is held for approximately 32 cycles before being turned off. this 32-cycle delay enables the cpu pipe and any other pending operations to flush properly. c. the device is now in standby mode. d. the external wake-up signal is driven active (negative edge triggered shown as an example). e. after a latency period, the standby mode is exited. f. normal operation resumes. the device will respond to the interrupt (if enabled). figure 6?15. standby entry and exit timing table 6?14. halt mode timing requirements min nom max unit t w(wake-xnmi) pulse duration, xnmi wakeup signal 2 * t c(ci) cycles t w(wake-xrs) pulse duration, xrs wakeup signal 8 * t c(ci) cycles electrical specifications 109 april 2001 ? revised december 2004 sprs174l table 6?15. halt mode switching characteristics parameter min typ max unit t d(idle-xcoh) delay time, idle instruction executed to xclkout high 32 * t c(sco) 4 5 * t c(sco) cycles t p pll lock-up time 131 072 * t c(ci) cycles delay time, pll lock to program execution resume t d(wake) ? wake-up from flash ? flash module in sleep state 1125*tc(sco) cycles ? wake-up from saram 35*tc(sco) cycles ? xclkout = sysclkout notes: a. idle instruction is executed to put the device into halt mode. b. the pll block responds to the halt signal. sysclkout is held for another 32 cycles before the oscillator is turned off and th e clkin to the core is stopped. this 32-cycle delay enables the cpu pipe and any other pending operations to flush properly. c. clocks to the device are turned off and the internal oscillator and pll are shut down. the device is now in halt mode and consumes absolute minimum power. d. when xnmi is driven active (negative edge triggered shown , as an example), the oscillator is turned on; but the pll is not activated. e. when xnmi is deactivated, it initiates the pll lock sequence, which takes 131,072 x1/xclkin cycles. f. when clkin to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. the halt mode is now exited. g. normal operation resumes. t d(idle?xcoh) 32 sysclkout cycles x1/xclkin xclkout ? halt halt wake-up latency flushing pipeline t d(wake) a b c d device status e g f pll lock-up time xnmi normal execution t w(wake-xnmi) t p oscillator start-up time figure 6?16. halt wakeup using xnmi electrical specifications 110 april 2001 ? revised december 2004 sprs174l 6.17 event manager interface 6.17.1 pwm timing pwm refers to all pwm outputs on eva and evb. table 6?16. pwm switching characteristics ?? parameter test conditions min max unit t w(pwm) pulse duration, pwmx output high/low 25 ns t d(pwm)xco delay time, xclkout high to pwmx output switching xclkout = sysclkout/4 10 ns ? see the gpio output timing for fall/rise times for pwm pins. ? pwm pin toggling frequency is limited by the gpio output buffer switching frequency (20 mhz). pwm outputs may be 100%, 0%, or increments of t c(hco) with respect to the pwm period. table 6?17. timer and capture unit timing requirements ?# min max unit t w(tdir) pulse duration, tdirx low/high without input qualifier 2 * t c(sco) cycles t w(tdir) pulse duration, tdirx low/high with input qualifier 1 * t c(sco) + iqt || cycles t w(cap) pulse duration, capx input low/high without input qualifier 2 * t c(sco) cycles t w(cap) pulse duration, capx input low/high with input qualifier 1 * t c(sco) + iqt || cycles t w(tclkinl) pulse duration, tclkinx low as a percentage of tclkinx cycle time 40 60 % t w(tclkinh) pulse duration, tclkinx high as a percentage of tclkinx cycle time 40 60 % t c(tclkin) cycle time, tclkinx 4 * t c(hco) ns ? the qualprd bit field value can range from 0 (no qualification) through 0xff (510 sysclkout cycles). the qualification sampling period is 2n sysclkout cycles, where ?n? is the value stored in the qualprd bit field. as an example, when qualprd = 1, the qualification sampling period is 1 x 2 = 2 sysclkout cycles (i.e., the input is sampled every 2 sysclkout cycles). six such samples will be taken over five sampling windows, each window being 2n sysclkout cycles. for qualprd = 1, the minimum width that is needed is 5 x 2 = 10 sysclkout cycles. however, since the external signal is driven asynchronously, a 11-sysclkout-wide pulse ensures reliable recognition. # maximum input frequency to the qep = min[hspclk/2, 20 mhz] || input qualification time (iqt) = [5 x qualprd x 2] * t c(sco) t w(pwm) t d(pwm)xco pwmx xclkout ? ? xclkout = sysclkout figure 6?17. pwm output timing xclkout ? t w(tdir) tdirx ? xclkout = sysclkout figure 6?18. tdirx timing electrical specifications 111 april 2001 ? revised december 2004 sprs174l table 6?18. external adc start-of-conversion ? eva ? switching characteristics ? parameter min max unit t d(xcoh-evasocl) delay time, xclkout high to evasoc low 1 * t c(sco) cycle t w(evasocl) pulse duration, evasoc low 32 * t c(hco) ns ? xclkout = sysclkout xclkout t d(xcoh-evasocl) evasoc t w(evasocl) figure 6?19. evasoc timing table 6?19. external adc start-of-conversion ? evb ? switching characteristics ? parameter min max unit t d(xcoh-evbsocl) delay time, xclkout high to evbsoc low 1 * t c(sco) cycle t w(evbsocl) pulse duration, evbsoc low 32 * t c(hco) ns ? xclkout = sysclkout xclkout t d(xcoh-evbsocl) evbsoc t w(evbsocl) figure 6?20. evbsoc timing electrical specifications 112 april 2001 ? revised december 2004 sprs174l 6.17.2 interrupt timing table 6?20. interrupt switching characteristics parameter min max unit t d(pdp-pwm)hz delay time, pdpintx low to pwm high-impedance state without input qualifier 12 ns t d(pdp-pwm)hz high-impedance state with input qualifier 1 * t c(sco) + iqt + 12 ? ns t d(trip-pwm)hz delay time, cxtrip /txctrip signals low to pwm without input qualifier 3 * t c(sco) ns t d(trip-pwm)hz signals low to pwm high-impedance state with input qualifier [2 * t c(sco) ] + iqt ? ns t d(int) delay time, int low/high to interrupt-vector fetch t qual + 12t c(xco) ns ? input qualification time (iqt) = [5 x qualprd x 2] * t c(sco) table 6?21. interrupt timing requirements min max unit t w(int) pulse duration, int input low/high with no qualifier 2 * t c(sco) cycles t w(int) pulse duration, int input low/high with qualifier 1 * t c(sco) + iqt ? cycles t w(pdp) pulse duration, pdpintx input low with no qualifier 2 * t c(sco) cycles t w(pdp) pulse duration, pdpintx input low with qualifier 1 * t c(sco) + iqt ? cycles t w(cxtrip) pulse duration, cxtrip input low with no qualifier 2 * t c(sco) cycles t w(cxtrip) pulse duration, cxtrip input low with qualifier 1 * t c(sco) + iqt ? cycles t w(txctrip) pulse duration, txctrip input low with no qualifier 2 * t c(sco) cycles t w(txctrip) pulse duration, txctrip input low with qualifier 1 * t c(sco) + iqt ? cycles ? input qualification time (iqt) = [5 x qualprd x 2] * t c(sco) electrical specifications 113 april 2001 ? revised december 2004 sprs174l pwm txctrip , cxtrip , pdpintx ? xclkout ? t w(pdp) , t w(cxtrip) , t w(txctrip) t d(pdp-pwm)hz , t d(trip-pwm)hz xnmi, xint1, xint2 t w(int) interrupt vector t d(int) ? xclkout = sysclkout ? txctrip ? t1ctrip , t2ctrip , t3ctrip , t4ctrip cxtrip ? c1trip , c2trip , c3trip , c4trip , c5trip , or c6trip pdpintx ? pdpinta or pdpintb pwm refers to all the pwm pins in the device (i.e., pwmn and tnpwm pins or pwm pin pair relevant to each cxtrip pin). the state of the pwm pins after pdpintx is taken high depends on the state of the fcompoe bit. a0?a15 figure 6?21. external interrupt timing 6.18 general-purpose input/output (gpio) ? output timing table 6?22. general-purpose output switching characteristics parameter min max unit t d(xcoh-gpo) delay time, xclkout high to gpio low/high all gpios 1 * t c(sco) cycle t d(xcoh-gpo) delay time, xclkout high to gpio low/high all gpios 1 * t c(sco) cycle t r(gpo) rise time, gpio switching low to high all gpios 10 ns t f(gpo) fall time, gpio switching high to low all gpios 10 ns f gpo toggling frequency, gpo pins 20 mhz t d(xcoh-gpo) gpio xclkout t r(gpo) t f(gpo) figure 6?22. general-purpose output timing electrical specifications 114 april 2001 ? revised december 2004 sprs174l 6.19 general-purpose input/output (gpio) ? input timing gpio signal 1 sampling window qualprd output from qualifier 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 sysclkout qualprd = 1 (2 x sysclkout cycles) x 5 notes: a. this glitch will be ignored by the input qualifier. the qualprd bit field specifies the qualification sampling period. it can vary from 00 to 0xff. input qualification is not applicable when qualprd = 00. for any other value ?n?, the qualification sampling period in 2n sysclkout cycles (i.e., at every 2n sysclkout cycle, the gpio pin will be sampled). six consecutive samples must be of the same value for a given input to be recognized. b. for the qualifier to detect the change, the input should be stable for 10 sysclkout cycles or greater. in other words, the in puts should be stable for (5 x qualprd x 2) sysclkout cycles. this would ensure six sampling windows for detection to occur. since external signals are driven asynchronously, an 11-sysclkout-wide pulse ensures reliable recognition. see note a figure 6?23. gpio input qualifier ? example diagram for qualprd = 1 table 6?23. general-purpose input timing requirements min max unit t w(gpi) pulse duration, gpio low/high all gpios with no qualifier 2 * t c(sco) cycles t w(gpi) pulse duration, gpio low/high all gpios with qualifier 1 * t c(sco) + iqt ? cycles ? input qualification time (iqt) = [5 x qualprd x 2] * t c(sco) gpioxn xclkout t w(gpi) figure 6?24. general-purpose input timing note: the pulse width requirement for general-purpose input is applicable for the xbio and adcsoc pins as well. electrical specifications 115 april 2001 ? revised december 2004 sprs174l 6.20 spi master mode timing table 6?24. spi master mode external timing (clock phase = 0) ?? no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit no. min max min max unit 1 t c(spc)m cycle time, spiclk 4t c(lco) 128t c(lco) 5t c(lco) 127t c(lco) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m ?0.5t c(lco) ?10 0.5t c(spc)m ?0.5t c(lco) ns 2 t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m ?0.5t c(lco) ?10 0.5t c(spc)m ? 0.5t c(lco) ns 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ?10 0.5t c(spc)m + 0.5t c(lco) ns 3 t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ?10 0.5t c(spc)m + 0.5t c(lco) ns 4 t d(spch-simo)m delay time, spiclk high to spisimo valid (clock polarity = 0) ? 10 10 ? 10 10 ns 4 t d(spcl-simo)m delay time, spiclk low to spisimo valid (clock polarity = 1) ? 10 10 ? 10 10 ns 5 t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m + 0.5t c(lco) ?10 ns 5 t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m + 0.5t c(lco) ?10 ns 8 t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 0) 0 0 ns 8 t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 1) 0 0 ns 9 t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 0) 0.25t c(spc)m ?10 0.5t c(spc)m ?0.5t c(lco) ?10 ns 9 t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 1) 0.25t c(spc)m ?10 0.5t c(spc)m ?0.5t c(lco) ?10 ns ? the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is cleared. ? t c(spc) = spi clock cycle time = lspclk 4 or lspclk (spibrr 1) t c(lco) = lspclk cycle time the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). note: internal clock prescalers must be adjusted such that the spi clock speed is not greater than the i/o buffer speed limit (2 0 mhz). electrical specifications 116 april 2001 ? revised december 2004 sprs174l 9 4 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 8 5 3 2 1 spiste ? ? in the master mode, spiste goes active 0.5t c(spc) before valid spi clock edge. on the trailing end of the word, the spiste will go inactive 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6?25. spi master mode external timing (clock phase = 0) electrical specifications 117 april 2001 ? revised december 2004 sprs174l table 6?25. spi master mode external timing (clock phase = 1) ?? no. spi when (spibrr + 1) is even or spibrr = 0 or 2 spi when (spibrr + 1) is odd and spibrr > 3 unit no. min max min max unit 1 t c(spc)m cycle time, spiclk 4t c(lco) 128t c(lco) 5t c(lco) 127t c(lco) ns 2 t w(spch)m pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m ?0.5t c(lco) ?10 0.5t c(spc)m ? 0.5t c(lco) ns 2 t w(spcl)m pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m ?0.5t c(lco) ?10 0.5t c(spc)m ? 0.5t c(lco) ns 3 t w(spcl)m pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ?10 0.5t c(spc)m + 0.5t c(lco) ns 3 t w(spch)m pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m 0.5t c(spc)m + 0.5t c(lco) ?10 0.5t c(spc)m + 0.5t c(lco) ns 6 t su(simo-spch)m setup time, spisimo data valid before spiclk high (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m ?10 ns 6 t su(simo-spcl)m setup time, spisimo data valid before spiclk low (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m ?10 ns 7 t v(spch-simo)m valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)m ?10 0.5t c(spc)m ?10 ns 7 t v(spcl-simo)m valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)m ?10 0.5t c(spc)m ?10 ns 10 t su(somi-spch)m setup time, spisomi before spiclk high (clock polarity = 0) 0 0 ns 10 t su(somi-spcl)m setup time, spisomi before spiclk low (clock polarity = 1) 0 0 ns 11 t v(spch-somi)m valid time, spisomi data valid after spiclk high (clock polarity = 0) 0.25t c(spc)m ?10 0.5t c(spc)m ?10 ns 11 t v(spcl-somi)m valid time, spisomi data valid after spiclk low (clock polarity = 1) 0.25t c(spc)m ?10 0.5t c(spc)m ?10 ns ? the master / slave bit (spictl.2) is set and the clock phase bit (spictl.3) is set. ? t c(spc) = spi clock cycle time = lspclk 4 or lspclk (spibrr 1) t c(lco) = lspclk cycle time the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). note: internal clock prescalers must be adjusted such that the spi clock speed is not greater than the i/o buffer speed limit (2 0 mhz). electrical specifications 118 april 2001 ? revised december 2004 sprs174l data valid 11 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 1 7 6 10 3 2 spiste ? ? in the master mode, spiste goes active 0.5t c(spc) before valid spi clock edge. on the trailing end of the word, the spiste will go inactive 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6?26. spi master external timing (clock phase = 1) electrical specifications 119 april 2001 ? revised december 2004 sprs174l 6.21 spi slave mode timing table 6?26. spi slave mode external timing (clock phase = 0) ?? no. min max unit 12 t c(spc)s cycle time, spiclk 4t c(lco) ? ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s ?10 0.5t c(spc)s ns 13 t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s ?10 0.5t c(spc)s ns 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s ?10 0.5t c(spc)s ns 14 t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s ?10 0.5t c(spc)s ns 15 t d(spch-somi)s delay time, spiclk high to spisomi valid (clock polarity = 0) 0.375t c(spc)s ?10 ns 15 t d(spcl-somi)s delay time, spiclk low to spisomi valid (clock polarity = 1) 0.375t c(spc)s ?10 ns 16 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =0) 0.75t c(spc)s ns 16 t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =1) 0.75t c(spc)s ns 19 t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 0) 0 ns 19 t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 1) 0 ns 20 t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 0) 0.5t c(spc)s ns 20 t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 1) 0.5t c(spc)s ns ? the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is cleared. ? t c(spc) = spi clock cycle time = lspclk 4 or lspclk (spibrr 1) t c(lco) = lspclk cycle time the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). electrical specifications 120 april 2001 ? revised december 2004 sprs174l 20 15 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 19 16 14 13 12 spiste ? ? in the slave mode, the spiste signal should be asserted low at least 0.5t c(spc) before the valid spi clock edge and remain low for at least 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6?27. spi slave mode external timing (clock phase = 0) electrical specifications 121 april 2001 ? revised december 2004 sprs174l table 6?27. spi slave mode external timing (clock phase = 1) ?? no. min max unit 12 t c(spc)s cycle time, spiclk 8t c(lco) ns 13 t w(spch)s pulse duration, spiclk high (clock polarity = 0) 0.5t c(spc)s ?10 0.5t c(spc)s ns 13 t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 0.5t c(spc)s ?10 0.5t c(spc)s ns 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 0.5t c(spc)s ?10 0.5t c(spc)s ns 14 t w(spch)s pulse duration, spiclk high (clock polarity = 1) 0.5t c(spc)s ?10 0.5t c(spc)s ns 17 t su(somi-spch)s setup time, spisomi before spiclk high (clock polarity = 0) 0.125t c(spc)s ns 17 t su(somi-spcl)s setup time, spisomi before spiclk low (clock polarity = 1) 0.125t c(spc)s ns 18 t v(spch-somi)s valid time, spisomi data valid after spiclk high (clock polarity =0) 0.75t c(spc)s ns 18 t v(spcl-somi)s valid time, spisomi data valid after spiclk low (clock polarity =1) 0.75t c(spc)s ns 21 t su(simo-spch)s setup time, spisimo before spiclk high (clock polarity = 0) 0 ns 21 t su(simo-spcl)s setup time, spisimo before spiclk low (clock polarity = 1) 0 ns 22 t v(spch-simo)s valid time, spisimo data valid after spiclk high (clock polarity = 0) 0.5t c(spc)s ns 22 t v(spcl-simo)s valid time, spisimo data valid after spiclk low (clock polarity = 1) 0.5t c(spc)s ns ? the master / slave bit (spictl.2) is cleared and the clock phase bit (spictl.3) is set. ? t c(spc) = spi clock cycle time = lspclk 4 or lspclk (spibrr 1) t c(lco) = lspclk cycle time the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spiccr.6). data valid 22 spisimo spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) spisimo data must be valid spisomi data is valid 21 12 18 17 14 13 spiste ? ? in the slave mode, the spiste signal should be asserted low at least 0.5t c(spc) before the valid spi clock edge and remain low for at least 0.5t c(spc) after the receiving edge (spiclk) of the last data bit. figure 6?28. spi slave mode external timing (clock phase = 1) electrical specifications 122 april 2001 ? revised december 2004 sprs174l 6.22 external interface (xintf) timing each xintf access consists of three parts: lead, active, and trail. the user configures the lead/active/t rail wait states in the xtiming registers. there is one xtiming register for each xintf zone. table 6?28 shows the relationship between the parameters configured in the xtiming register and the duration of the pulse in terms of xtimclk cycles. table 6?28. relationship between parameters configured in xtiming and duration of pulse ?? description duration (ns) description x2timing = 0 x2timing = 1 lr lead period, read access xrdlead x t c(xtim) (xrdlead x 2) x t c(xtim) ar active period, read access (xrdactive + ws + 1) x t c(xtim) (xrdactive x 2 + ws + 1) x t c(xtim) tr trail period, read access xrdtrail x t c(xtim) (xrdtrail x 2) x t c(xtim) lw lead period, write access xwrlead x t c(xtim) (xwrlead x 2) x t c(xtim) aw active period, write access (xwractive + ws + 1) x t c(xtim) (xwractive x 2 + ws + 1) x t c(xtim) tw trail period, write access xwrtrail x t c(xtim) (xwrtrail x 2) x t c(xtim) ? t c(xtim) ? cycle time, xtimclk ? ws refers to the number of wait states inserted by hardware when using xready. if the zone is configured to ignore xready (user eady = 0), then ws = 0. minimum wait state requirements must be met when configuring each zone?s xtiming register. these requirements are in addition to any timing requirements as specified by that device?s data sheet. no internal device hardware is included to detect illegal settings. ? if the xready signal is ignored (useready = 0), then: 1. lead: lr t c(xtim) lw t c(xtim) these requirements result in the following xtiming register configuration restrictions : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing 1 0 0 1 0 0 0, 1 no hardware to detect illegal xtiming configurations examples of valid and invalid timing when not sampling xready : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing invalid 0 0 0 0 0 0 0, 1 valid 1 0 0 1 0 0 0, 1 no hardware to detect illegal xtiming configurations electrical specifications 123 april 2001 ? revised december 2004 sprs174l ? if the xready signal is sampled in the synchronous mode (useready = 1, readymode = 0), then: 1. lead: lr t c(xtim) lw t c(xtim) 2. active: ar 2 x t c(xtim) aw 2 x t c(xtim) note : restriction does not include external hardware wait states these requirements result in the following xtiming register configuration restrictions ? : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing 1 1 0 1 1 0 0, 1 ? no hardware to detect illegal xtiming configurations examples of valid and invalid timing when using synchronous xready ? : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing invalid 0 0 0 0 0 0 0, 1 invalid 1 0 0 1 0 0 0, 1 valid 1 1 0 1 1 0 0, 1 ? no hardware to detect illegal xtiming configurations ? if the xready signal is sampled in the asynchronous mode (useready = 1, readymode = 1), then: 1. lead: lr t c(xtim) lw t c(xtim) 2. active: ar 2 x t c(xtim) aw 2 x t c(xtim) note : restriction does not include external hardware wait states 3. lead + active: lr + ar 4 x t c(xtim) lw + aw 4 x t c(xtim) note : restriction does not include external hardware wait states these requirements result in the following xtiming register configuration restrictions ? : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing 1 2 0 1 2 0 0, 1 ? no hardware to detect illegal xtiming configurations or ? xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing 2 1 0 2 1 0 0, 1 ? no hardware to detect illegal xtiming configurations examples of valid and invalid timing when using asynchronous xready ? : xrdlead xrdactive xrdtrail xwrlead xwractive xwrtrail x2timing invalid 0 0 0 0 0 0 0, 1 invalid 1 0 0 1 0 0 0, 1 invalid 1 1 0 1 1 0 0 valid 1 1 0 1 1 0 1 valid 1 2 0 1 2 0 0, 1 valid 2 1 0 2 1 0 0, 1 ? no hardware to detect illegal xtiming configurations electrical specifications 124 april 2001 ? revised december 2004 sprs174l unless otherwise specified, all xintf timing is applicable for the clock configurations shown in table 6?29. table 6?29. xintf clock configurations mode sysclkout xtimclk xclkout 1 example: 150 mhz sysclkout 150 mhz sysclkout 150 mhz 2 example: 150 mhz sysclkout 150 mhz 1/2 sysclkout 75 mhz 3 example: 150 mhz 1/2 sysclkout 75 mhz 1/2 sysclkout 75 mhz 4 example: 150 mhz 1/2 sysclkout 75 mhz 1/4 sysclkout 37.5 mhz the relationship between sysclkout and xtimclk is shown in figure 6?29. xtiming0 xtiming1 xtiming2 xtiming6 xtiming7 xbank lead/active/trail 1 ? 0 xclkout /2 xtimclk 1 ? 0 /2 c28x cpu xintcnf2 (clkmode) xintcnf2 (xtimclk) ? default value after reset sysclkout xintcnf2 (clkoff) 1 0 0 figure 6?29. relationship between xtimclk and sysclkout 6.23 xintf signal alignment to xclkout for each xintf access, the number of lead, active, and trail cycles is based on the internal clock xtimclk. strobes such as xrd , xwe , and zone chip-select (xzcs) change state in relationship to the rising edge of xtimclk. the external clock, xclkout, can be configured to be either equal to or one-half the frequency of xtimclk. for the case where xclkout = xtimclk, all of the xintf strobes will change state with respect to the rising edge of xclkout. for the case where xclkout = one-half xtimclk, some strobes will change state either on the rising edge of xclkout or the falling edge of xclkout. in the xintf timing tables, the notation xcohl is used to indicate that the parameter is with respect to either case; xclkout rising edge (high) or xclkout falling edge (low). if the parameter is always with respect to the rising edge of xclkout, the notation xcoh is used. electrical specifications 125 april 2001 ? revised december 2004 sprs174l for the case where xclkout = one-half xtimclk, the xclkout edge with which the change will be aligned can be determined based on the number of xtimclk cycles from the start of the access to the point at which the signal changes. if this number of xtimclk cycles is even, the alignment will be with respect to the rising edge of xclkout. if this number is odd, then the signal will change with respect to the falling edge of xclkout. examples include the following: ? strobes that change at the beginning of an access always align to the rising edge of xclkout. this is because all xintf accesses begin with respect to the rising edge of xclkout. examples: xzcsl zone chip-select active low xrnwl xr/w active low ? strobes that change at the beginning of the active period will align to the rising edge of xclkout if the total number of lead xtimclk cycles for the access is even. if the number of lead xtimclk cycles is odd, then the alignment will be with respect to the falling edge of xclkout. examples: xrdl xrd active low xwel xwe active low ? strobes that change at the beginning of the trail period will align to the rising edge of xclkout if the total number of lead + active xtimclk cycles (including hardware waitstates) for the access is even. if the number of lead + active xtimclk cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of xclkout. examples: xrdh xrd inactive high xweh xwe inactive high ? strobes that change at the end of the access will align to the rising edge of xclkout if the total number of lead + active + trail xtimclk cycles (including hardware waitstates) is even. if the number of lead + active + trail xtimclk cycles (including hardware waitstates) is odd, then the alignment will be with respect to the falling edge of xclkout. examples: xzcsh zone chip-select inactive high xrnwh xr/w inactive high electrical specifications 126 april 2001 ? revised december 2004 sprs174l 6.24 external interface read timing table 6?30. external memory interface read switching characteristics parameter min max unit t d(xcoh-xzcsl) delay time, xclkout high to zone chip-select active low 1 ns t d(xcohl-xzcsh) delay time, xclkout high/low to zone chip-select inactive high ?2 3 ns t d(xcoh-xa) delay time, xclkout high to address valid 2 ns t d(xcohl-xrdl) delay time, xclkout high/low to xrd active low 1 ns t d(xcohl-xrdh delay time, xclkout high/low to xrd inactive high ?2 1 ns t h(xa)xzcsh hold time, address valid after zone chip-select inactive high ? ns t h(xa)xrd hold time, address valid after xrd inactive high ? ns ? during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cyc les. table 6?31. external memory interface read timing requirements min max unit t a(a) access time, read data from address valid (lr + ar) ? 14 ? ns t a(xrd) access time, read data valid from xrd active low ar ? 12 ? ns t su(xd)xrd setup time, read data valid before xrd strobe inactive high 12 ns t h(xd)xrd hold time, read data valid after xrd inactive high 0 ns ? lr = lead period, read access. ar = active period, read access. see table 6?28. lead active trail din t d(xcohl-xrdl) t d(xcoh-xa) t d(xcoh-xzcsl) t d(xcohl-xrdh) t h(xd)xrd t d(xcohl-xzcsh) xclkout=xtimclk xclkout=1/2 xtimclk xzcs0and1 , xzcs2 , xzcs6and7 xa[0:18] xrd xwe xr/w xd[0:15] notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignment cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. for useready = 0, the external xready input signal is ignored. d. xa[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles. t su(xd)xrd t a(a) t a(xrd) xready figure 6?30. example read access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode 1 0 0 0 0 n/a ? n/a ? n/a ? n/a ? ? n/a = ?don?t care? for this example electrical specifications 127 april 2001 ? revised december 2004 sprs174l 6.25 external interface write timing table 6?32. external memory interface write switching characteristics parameter min max unit t d(xcoh-xzcsl) delay time, xclkout high to zone chip-select active low 1 ns t d(xcohl-xzcsh) delay time, xclkout high or low to zone chip-select inactive high ?2 3 ns t d(xcoh-xa) delay time, xclkout high to address valid 2 ns t d(xcohl-xwel) delay time, xclkout high/low to xwe low 2 ns t d(xcohl-xweh) delay time, xclkout high/low to xwe high 2 ns t d(xcoh-xrnwl) delay time, xclkout high to xr/w low 1 ns t d(xcohl-xrnwh) delay time, xclkout high/low to xr/w high ?2 1 ns t en(xd)xwel enable time, data bus driven from xwe low 0 ns t d(xwel-xd) delay time, data valid after xwe active low 4 ns t h(xa)xzcsh hold time, address valid after zone chip-select inactive high ? ns t h(xd)xwe hold time, write data valid after xwe inactive high tw?2 ? ns t dis(xd)xrnw data bus disabled after xr/w inactive high 4 ns ? during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cyc les. ? tw = trail period, write access. see table 6?28. lead active trail t d(xcoh-xzcsl) t d(xcoh-xa) t d(xcohl-xwel) t d(xcohl-xweh) t d(xcohl-xzcsh) t en(xd)xwel t h(xd)xweh t dis(xd)xrnw xclkout=xtimclk xclkout=1/2 xtimclk xzcs0and1 , xzcs2 , xzcs6and7 xa[0:18] xrd xwe xr/w xd[0:15] notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignme n t cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. for useready = 0, the external xready input signal is ignored. d. xa[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles. t d(xcoh-xrnwl) t d(xcohl-xrnwh) dout xready t d(xwel-xd) figure 6?31. example write access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode n/a ? n/a ? n/a ? 0 0 1 0 0 n/a ? ? n/a = ?don?t care? for this example electrical specifications 128 april 2001 ? revised december 2004 sprs174l 6.26 external interface ready-on-read timing with one external wait state table 6?33. external memory interface read switching characteristics (ready-on-read, 1 wait state) parameter min max unit t d(xcoh-xzcsl) delay time, xclkout high to zone chip-select active low 1 ns t d(xcohl-xzcsh) delay time, xclkout high/low to zone chip-select inactive high ?2 3 ns t d(xcoh-xa) delay time, xclkout high to address valid 2 ns t d(xcohl-xrdl) delay time, xclkout high/low to xrd active low 1 ns t d(xcohl-xrdh delay time, xclkout high/low to xrd inactive high ?2 1 ns t h(xa)xzcsh hold time, address valid after zone chip-select inactive high ? ns t h(xa)xrd hold time, address valid after xrd inactive high ? ns ? during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cyc les. table 6?34. external memory interface read timing requirements (ready-on-read, 1 wait state) min max unit t a(a) access time, read data from address valid (lr + ar) ? 14 ? ns t a(xrd) access time, read data valid from xrd active low ar ? 12 ? ns t su(xd)xrd setup time, read data valid before xrd strobe inactive high 12 ns t h(xd)xrd hold time, read data valid after xrd inactive high 0 ns ? lr = lead period, read access. ar = active period, read access. see table 6?28. table 6?35. synchronous xready timing requirements (ready-on-read, 1 wait state) min max unit t su(xrdysynchl)xcohl setup time, xready (synch) low before xclkout high/low 15 ns t h(xrdysynchl) hold time, xready (synch) low 12 ns t e(xrdysynchh) earliest time xready (synch) can go high before the sampling xclkout edge 3 ns t su(xrdysynchh)xcohl setup time, xready (synch) high before xclkout high/low 15 ns t h(xrdysynchh)xzcsh hold time, xready (synch) held high after zone chip select high 0 ns the first xready (synch) sample occurs with respect to e in figure 6?32: e = (xrdlead + xrdactive) t c(xtim) when first sampled, if xready (synch) is found to be high, then the access will complete. if xready (synch) is found to be low, it w ill be sampled again each t c(xtim) until it is found to be high. for each sample (n) the setup time (d) with respect to the beginning of the access can be calculated as: d = (xrdlead + xrdactive +n ? 1) t c(xtim) ? t su(xrdysynchl)xcohl where n is the sample number: n = 1, 2, 3, and so forth. table 6?36. asynchronous xready timing requirements (ready-on-read, 1 wait state) ? min max unit t su(xrdyasynchl)xcohl setup time, xready (async) low before xclkout high/low 11 ns t h(xrdyasynchl) hold time, xready (async) low 8 ns t e(xrdyasynchh) earliest time xready (async) can go high before the sampling xclkout edge 3 ns t su(xrdyasynchh)xcohl setup time, xready (async) high before xclkout high/low 11 ns t h(xrdyasynchh)xzcsh hold time, xready (async) held high after zone chip select high 0 ns ? the first xready (async) sample occurs with respect to e in figure 6?33: e = (xrdlead + xrdactive ?2) t c(xtim) when first sampled, if xready (async) is found to be high, then the access will complete. if xready (async) is found to be low, it w ill be sampled again each t c(xtim) until it is found to be high. for each sample, setup time from the beginning of the access can be calculated as: d = (xrdlead + xrdactive ?3 +n) t c(xtim) ? t su(xrdyasynchl)xcohl where n is the sample number: n = 1, 2, 3, and so forth. electrical specifications 129 april 2001 ? revised december 2004 sprs174l lead active trail din t d(xcoh-xzcsl) t d(xcoh-xa) t d(xcohl-xrdl) t d(xcohl-xzcsh) t d(xcohl-xrdh) ws (synch) xclkout=xtimclk xclkout=1/2 xtimclk xzcs0and1 , xzcs2 , xzcs6and7 xa[0:18] xrd xwe xr/w xd[0:15] xready(synch) notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignment cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cycles. d. for each sample, setup time from the beginning of the access (d) can be calculated as: d = (xrdlead + xrdactive +n ? 1) t c(xtim) ? t su(xrdysynchl)xcohl e. reference for the first sample is with respect to this point e = (xrdlead + xrdactive) t c(xtim) where n is the sample number: n = 1, 2, 3, and so forth. t h(xrdysynchl) t su(xrdysynchl)xcohl t su(xd)xrd t a(xrd) t a(a) t h(xd)xrd t h(xrdysynchh)xzcsh = don?t care. signal can be high or low during this time. legend: t su(xrdhsynchh)xcohl see note d see note e t e(xrdysynchh) see note d see notes a and b see note c figure 6?32. example read with synchronous xready access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode 1 3 1 1 0 n/a ? n/a ? n/a ? 0 = xready (synch) ? n/a = ?don?t care? for this example electrical specifications 130 april 2001 ? revised december 2004 sprs174l t su(xd)xrd lead active trail din t d(xcoh-xzcsl) t d(xcoh-xa) t d(xcohl-xrdl) t d(xcohl-xzcsh) t d(xcohl-xrdh) ws (async) xclkout=xtimclk xclkout=1/2 xtimclk xzcs0and1 , xzcs2 , xzcs6and7 xa[0:18] xrd xwe xr/w xd[0:15] xready(asynch) notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignme nt cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cycles. d. for each sample, setup time from the beginning of the access can be calculated as: d = (xrdlead + xrdactive ?3 +n) t c(xtim) ? t su(xrdyasynchl)xcohl where n is the sample number: n = 1, 2, 3, and so forth. e. reference for the first sample is with respect to this point: e = (xrdlead + xrdactive ?2) t c(xtim) t su(xrdyasynchl)xcohl t a(xrd) t a(a) t h(xrdyasynchl) t h(xd)xrd t h(xrdyasynchh)xzcsh = don?t care. signal can be high or low during this time. legend: see note c t su(xrdyasynchh)xcohl see note d see note e t e(xrdyasynchh) figure 6?33. example read with asynchronous xready access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode 1 3 1 1 0 n/a ? n/a ? n/a ? 1 = xready (async) ? n/a = ?don?t care? for this example electrical specifications 131 april 2001 ? revised december 2004 sprs174l 6.27 external interface ready-on-write timing with one external wait state table 6?37. external memory interface write switching characteristics (ready-on-write, 1 wait state) parameter min max unit t d(xcoh-xzcsl) delay time, xclkout high to zone chip-select active low 1 ns t d(xcohl-xzcsh) delay time, xclkout high or low to zone chip-select inactive high ?2 3 ns t d(xcoh-xa) delay time, xclkout high to address valid 2 ns t d(xcohl-xwel) delay time, xclkout high/low to xwe low 2 ns t d(xcohl-xweh) delay time, xclkout high/low to xwe high 2 ns t d(xcoh-xrnwl) delay time, xclkout high to xr/w low 1 ns t d(xcohl-xrnwh) delay time, xclkout high/low to xr/w high ?2 1 ns t en(xd)xwel enable time, data bus driven from xwe low 0 ns t d(xwel-xd) delay time, data valid after xwe active low 4 ns t h(xa)xzcsh hold time, address valid after zone chip-select inactive high ? ns t h(xd)xwe hold time, write data valid after xwe inactive high tw?2 ? ns t dis(xd)xrnw data bus disabled after xr/w inactive high 4 ns ? during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cyc les. ? tw = trail period, write access (see table 6?28) table 6?38. synchronous xready timing requirements (ready-on-write, 1 wait state) min max unit t su(xrdysynchl)xcohl setup time, xready (synch) low before xclkout high/low 15 ns t h(xrdysynchl) hold time, xready (synch) low 12 ns t e(xrdysynchh) earliest time xready (synch) can go high before the sampling xclkout edge 3 ns t su(xrdysynchh)xcohl setup time, xready (synch) high before xclkout high/low 15 ns t h(xrdysynchh)xzcsh hold time, xready (synch) held high after zone chip select high 0 ns the first xready (synch) sample occurs with respect to e in figure 6?34: e =(xwrlead + xwractive) t c(xtim) when first sampled, if xready (synch) is found to be high, then the access will complete. if xready (synch) is found to be low, it w ill be sampled again each t c(xtim) until it is found to be high. for each sample, setup time from the beginning of the access can be calculated as: d =(xwrlead + xwractive +n ? 1) t c(xtim) ? t su(xrdysynchl)xcohl where n is the sample number: n = 1, 2, 3, and so forth. table 6?39. asynchronous xready timing requirements (ready-on-write, 1 wait state) ? min max unit t su(xrdyasynchl)xcohl setup time, xready (async) low before xclkout high/low 11 ns t h(xrdyasynchl) hold time, xready (async) low 8 ns t e(xrdyasynchh) earliest time xready (async) can go high before the sampling xclkout edge 3 ns t su(xrdyasynchh)xcohl setup time, xready (async) high before xclkout high/low 11 ns t h(xrdyasynchh)xzcsh hold time, xready (async) held high after zone chip select high 0 ns ? the first xready (synch) sample occurs with respect to e in figure 6?35: e = (xwrlead + xwractive ? 2) t c(xtim) when first sampled, if xready (async) is found to be high, then the access will complete. if xready (async) is found to be low, it w ill be sampled again each t c(xtim) until it is found to be high. for each sample, setup time from the beginning of the access can be calculated as: d = (xwrlead + xwractive ?3 + n) t c(xtim) ? t su(xrdyasynchl)xcohl where n is the sample number: n = 1, 2, 3, and so forth. electrical specifications 132 april 2001 ? revised december 2004 sprs174l lead 1 active trail xclkout = xtimclk xclkout = 1/2 xtimclk xa[0:18] xd[0:15] xready(synch) t d(xcohl-xwel) t d(xcohl-xweh) t d(xcohl-xzcsh) t d(xcoh-xa) ws (synch) xzcs0and1 , xzcs2 , xzcs6and7 xrd xwe xr/w t d(xcoh-xzcsl) notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignme nt cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment c ycles. d. for each sample, setup time from the beginning of the access can be calculated as d = (xwrlead + xwractive + n ? 1) t c(xtim) ? t su(xrdysynchl)xcohl where n is the sample number: n = 1, 2, 3 and so forth. e. reference for the first sample is with respect to this point e = (xwrlead + xwractive) t c(xtim) t d(xcoh-xrnwl) t d(xcohl-xrnwh) t en(xd)xwel t h(xd)xweh t su(xrdhsynchh)xcohl t su(xrdysynchl)xcohl dout t d(xwel-xd) t dis(xd)xrnw t h(xrdysynchl) t h(xrdysynchh)xzcsh = don?t care. signal can be high or low during this time. legend: see note e see note d see notes a and b see note c t e(xrdysynchh) figure 6?34. write with synchronous xready access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode n/a ? n/a ? n/a ? 1 0 1 3 1 0 = xready (synch) electrical specifications 133 april 2001 ? revised december 2004 sprs174l lead 1 active trail xclkout = xtimclk xclkout = 1/2 xtimclk xa[0:18] xd[0:15] t d(xcohl-xweh) t d(xcohl-xzcsh) t d(xcoh-xa) ws (async) xzcs0and1 , xzcs2 , xzcs6and7 xrd xwe xr/w t d(xcoh-xzcsl) notes: a. all xintf accesses (lead period) begin on the rising edge of xclkout. when necessary, the device will insert an alignment cycle before an access to meet this requirement. b. during alignment cycles, all signals will transition to their inactive state. c. during inactive cycles, the xintf address bus will always hold the last address put out on the bus. this includes alignment cycles. d. for each sample, setup time from the beginning of the access can be calculated as: d = (xwrlead + xwractive ?3 + n) t c(xtim) ? t su(xrdyasynchl)xcohl where n is the sample number: n = 1, 2, 3 and so forth. e. reference for the first sample is with respect to this point e = (xwrlead + xwractive ?2) t c(xtim) t d(xcoh-xrnwl) t d(xcohl-xrnwh) t en(xd)xwel t h(xd)xweh t h(xrdyasynchl) dout t dis(xd)xrnw t h(xrdyasynchh)xzcsh see note e see note d = don?t care. signal can be high or low during this time. legend: t su(xrdyasynchl)xcohl t su(xrdyasynchh)xcohl t d(xwel-xd) t d(xcohl-xwel) t e(xrdyasynchh) xready(asynch) figure 6?35. write with asynchronous xready access xtiming register parameters used for this example: xrdlead xrdactive xrdtrail useready x2timing xwrlead xwractive xwrtrail readymode n/a ? n/a ? n/a ? 1 0 1 3 1 1 = xready (async) ? n/a = ?don?t care? for this example electrical specifications 134 april 2001 ? revised december 2004 sprs174l 6.28 xhold and xholda if the hold mode bit is set while xhold and xholda are both low (external bus accesses granted), the xholda signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode. on a reset (xrs ), the hold mode bit is set to 0. if the xhold signal is active low on a system reset, the bus and all signal strobes must be in high-impedance mode, and the xholda signal is also driven active low. when hold mode is enabled and xholda is active low (external bus grant active), the cpu can still execute code from internal memory. if an access is made to the external interface, the cpu is stalled until the xhold signal is removed. an external dma request, when granted, places the following signals in a high-impedance mode: xa[18:0] xzcs0and1 xd[15:0] xzcs2 xwe , xrd xzcs6and7 xr/w all other signals not listed in this group remain in their default or functional operational modes during these signal events. detailed timing diagram will be released in a future revision of this data sheet. electrical specifications 135 april 2001 ? revised december 2004 sprs174l 6.29 xhold /xholda timing table 6?40. xhold /xholda timing requirements (xclkout = xtimclk) ?? min max unit t d(hl-hiz) delay time, xhold low to hi-z on all address, data, and control 4t c(xtim) ns t d(hl-hal) delay time, xhold low to xholda low 5t c(xtim) ns t d(hh-hah) delay time, xhold high to xholda high 3t c(xtim) ns t d(hh-bv) delay time, xhold high to bus valid 4t c(xtim) ns ? when a low signal is detected on xhold , all pending xintf accesses will be completed before the bus is placed in a high-impedance state. ? the state of xhold is latched on the rising edge of xtimclk. xclkout (/1 mode) xhold xr/w , xzcs0and1 , xzcs2 , xzcs6and7 xd[15:0] valid xholda t d(hl-hiz) t d(hh-hah) high-impedance xa[18:0] valid valid high-impedance t d(hh-bv) t d(hl-hal) see note a see note b notes: a. all pending xintf accesses are completed. b. normal xintf operation resumes. figure 6?36. external interface hold waveform electrical specifications 136 april 2001 ? revised december 2004 sprs174l table 6?41. xhold /xholda timing requirements (xclkout = 1/2 xtimclk) ?? min max unit t d(hl-hiz) delay time, xhold low to hi-z on all address, data, and control 4t c(xtim)+ t c(xco) ns t d(hl-hal) delay time, xhold low to xholda low 4t c(xtim +2t c(xco) ns t d(hh-hah) delay time, xhold high to xholda high 4t c(xtim) ns t d(hh-bv) delay time, xhold high to bus valid 6t c(xtim) ns ? when a low signal is detected on xhold , all pending xintf accesses will be completed before the bus is placed in a high-impedance state. ? the state of xhold is latched on the rising edge of xtimclk. after the xhold is detected low or high, all bus transitions and xholda transitions will occur with respect to the rising edge of xclkout. thus, for this mode where xclkout = 1/2 xtimclk, the transitions can occur up to 1 xtimclk cycle earlier than the maximum value speci fied. xclkout (1/2 xtimclk) xhold xr/w , xzcs0and1 , xzcs2 , xzcs6and7 xd[15:0] valid xholda t d(hl-hiz) t d(hh-hah) high-impedance xa[18:0] valid valid high-impedance t d(hh-bv) t d(hl-hal) high-impedance see note a see note b notes: a all pending xintf accesses are completed. b normal xintf operation resumes. figure 6?37. xhold /xholda timing requirements (xclkout = 1/2 xtimclk) electrical specifications 137 april 2001 ? revised december 2004 sprs174l 6.30 on-chip analog-to-digital converter 6.30.1 adc absolute maximum ratings ? supply voltage range, v ssa1 /v ssa2 to v dda1 /v dda2 /av ddrefbg ?0.3 v to 4.6 v . . . . . . . . . . . . . . . v ss1 to v dd1 ?0.3 v to 2.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog input (adcin) clamp current, total (max) 20 ma ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? unless otherwise noted, the list of absolute maximum ratings are specified over operating conditions. stresses beyond those lis ted under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. exposure to absolute-maximum- rated conditions for extended periods may affect device reliability. ? the analog inputs have an internal clamping circuit that clamps the voltage to a diode drop above v dda or below v ss . the continuous clamp current per pin is 2 ma. electrical specifications 138 april 2001 ? revised december 2004 sprs174l 6.30.2 adc electrical characteristics over recommended operating conditions table 6?42. dc specifications (see note 1) parameter min typ max unit resolution 12 bits adc clock (see note 2) 1 khz adc clock (see note 2) 25 mhz accuracy inl (integral nonlinearity) (see note 3) 1?18.75 mhz adc clock 1.5 lsb dnl (differential nonlinearity) (see note 3) 1?18.75 mhz adc clock 1 lsb offset error (see note 4) ?80 80 lsb overall gain error with internal reference f281x ?200 200 lsb overall gain error with internal reference (see note 5) c281x ?80 80 lsb overall gain error with external reference (see note 6) if adcrefp?adcrefm = 1 v 0.1% ?50 50 lsb channel-to-channel offset variation 8 lsb channel-to-channel gain variation 8 lsb analog input analog input voltage (adcinx to adclo) (see note 7) 0 3 v adclo ?5 0 5 mv input capacitance 10 pf input leakage current 3 5 a internal voltage reference (see note 5) accuracy, adcv refp 1.9 2 2.1 v accuracy, adcv refm 0.95 1 1.05 v voltage difference, adcrefp ? adcrefm 1 v temperature coefficient 50 ppm/ c reference noise 100 v external voltage reference (see note 6) accuracy, adcv refp 1.9 2 2.1 v accuracy, adcv refm 0.95 1 1.05 v input voltage difference, adcrefp ? adcrefm 0.99 1 1.01 v notes: 1. tested at 12.5-mhz adcclk 2. if sysclkout 25 mhz, adc clock sysclkout/2 3. the inl degrades for frequencies beyond 18.75 mhz ? 25 mhz. applications that require these sampling rates should use a 20k-resistor as bias resistor on the adcresext pin. this improves overall linearity and typical current drawn by the adc will be a few ma more than 24.9 k ? bias. the adc module in c281x devices can operate at 24.9k bias on adcresext pin for the full range 1?25mhz 4. 1 lsb has the weighted value of 3.0/4096 = 0.732 mv. 5. a single internal band gap reference ( 5% accuracy) sources both adcrefp and adcrefm signals, and hence, these voltages track together. the adc converter uses the difference between these two as its reference. the total gain error will be the combination of the gain error shown here and the voltage reference accuracy (adcrefp ? adcrefm). a software-based calibration procedure is recommended for better accuracy. see f2812 adc calibration application note (literature number spra989) and section 5.2, documentation support, for relevant documents. 6. in this mode, the accuracy of external reference is critical for overall gain. the voltage difference (adcrefp?adcrefm) will determine the overall accuracy. 7. voltages above v dda + 0.3 v or below v ss ? 0.3 v applied to an analog input pin may temporarily affect the conversion of another pin. to avoid this, the analog inputs should be kept within these limits. electrical specifications 139 april 2001 ? revised december 2004 sprs174l table 6?43. ac specifications parameter min typ max unit sinad signal-to-noise ratio + distortion 62 db snr signal-to-noise ratio 62 db thd (100 khz) total harmonic distortion ?68 db enob (snr) effective number of bits 10.1 bits sfdr spurious free dynamic range 69 db 6.30.3 current consumption for different adc configurations (at 25-mhz adcclk) ? i dda (typ) i ddaio (typ) i dd1 (typ) adc operating mode/conditions 40 ma 1 a 0.5 ma mode a (operational mode): ? bg and ref enabled ? pwd disabled 7 ma 0 5 a mode b: ? adc clock enabled ? bg and ref enabled ? pwd enabled 1 a 0 5 a mode c: ? adc clock enabled ? bg and ref disabled ? pwd enabled 1 a 0 0 mode d: ? adc clock disabled ? bg and ref disabled ? pwd enabled ? test conditions: sysclkout = 150 mhz adc module clock = 25 mhz adc performing a continuous conversion of all 16 channels in mode a i dda ? includes current into v dda1 /v dda2 and av ddrefbg electrical specifications 140 april 2001 ? revised december 2004 sprs174l ac r s adcin0 c p 10 pf r on 1 k ? 1.25 pf c h switch typical values of the input circuit components: switch resistance (r on ): 1 k ? sampling capacitor (c h ): 1.25 pf parasitic capacitance (c p ): 10 pf source resistance (r s ): 50 ? 28x dsp source signal figure 6?38. adc analog input impedance model 6.30.4 adc power-up control bit timing adc power up delay adc ready for conversions pwdnbg pwdnref pwdnadc r equest for adc conversion t d(bgr) t d(pwd) figure 6?39. adc power-up control bit timing table 6?44. adc power-up delays ? min typ max unit t d(bgr) delay time for band gap reference to be stable. bits 6 and 5 of the adctrl3 register (pwdnbg and pwdnref) are to be set to 1 before the adcpwdn bit is enabled. 7 8 10 ms t d(pwd) delay time for power-down control to be stable. bit 7 of the adctrl3 register 20 50 s t d(pwd) delay time for power-down control to be stable. bit 7 of the adctrl3 register (adcpwdn) is to be set to 1 before any adc conversions are initiated. 1 ms ? these delays are necessary and recommended to make the adc analog reference circuit stable before conversions are initiated. if conve rsions are started without these delays, the adc results will show a higher gain. for power down, all three bits can be cleared at the same time. electrical specifications 141 april 2001 ? revised december 2004 sprs174l 6.30.5 detailed description 6.30.5.1 reference voltage the on-chip adc has a built-in reference, which provides the reference voltages for the adc. adcvrefp is set to 2.0 v and adcvrefm is set to 1.0 v. 6.30.5.2 analog inputs the on-chip adc consists of 16 analog inputs, which are sampled either one at a time or two channels at a time. these inputs are software-selectable. 6.30.5.3 converter the on-chip adc uses a 12-bit four-stage pipeline architecture, which achieves a high sample rate with low power consumption. 6.30.5.4 conversion modes the conversion can be performed in two different conversion modes: ? sequential sampling mode (smode = 0) ? simultaneous sampling mode (smode = 1) 6.30.6 sequential sampling mode (single-channel) (smode = 0) in sequential sampling mode, the adc can continuously convert input signals on any of the channels (ax to bx). the adc can start conversions on event triggers from the event managers (eva/evb), software trigger, or from an external adcsoc signal. if the smode bit is 0, the adc will do conversions on the selected channel on every sample/hold pulse. the conversion time and latency of the result register update are explained below. the adc interrupt flags are set a few sysclkout cycles after the result register update. the selected channels will be sampled at every falling edge of the sample/hold pulse. the sample/hold pulse width can be programmed to be 1 adc clock wide (minimum) or 16 adc clocks wide (maximum). electrical specifications 142 april 2001 ? revised december 2004 sprs174l analog input on channel ax or bx adc clock sample and hold sh pulse smode bit t dschx_n t dschx_n+1 sample n sample n+1 sample n+2 t sh adc event trigger from ev or other sources t d(sh) figure 6?40. sequential sampling mode (single-channel) timing table 6?45. sequential sampling mode timing sample n sample n + 1 at 25-mhz adc clock, t c(adcclk) = 40 ns remarks t d(sh) delay time from event trigger to sampling 2.5t c(adcclk) t sh sample/hold width/ acquisition width (1 + acqps) * t c(adcclk) 40 ns with acqps = 0 acqps value = 0?15 adctrl1[8:11] t d(schx_n) delay time for first result to appear in the result register 4t c(adcclk) 160 ns t d(schx_n+1) delay time for successive results to appear in the result register (2 + acqps) * t c(adcclk) 80 ns electrical specifications 143 april 2001 ? revised december 2004 sprs174l 6.30.7 simultaneous sampling mode (dual-channel) (smode = 1) in simultaneous mode, the adc can continuously convert input signals on any one pair of channels (a0/b0 to a7/b7). the adc can start conversions on event triggers from the event managers (eva/evb), software trigger, or from an external adcsoc signal. if the smode bit is 1, the adc will do conversions on two selected channels on every sample/hold pulse. the conversion time and latency of the result register update are explained below. the adc interrupt flags are set a few sysclkout cycles after the result register update. the selected channels will be sampled simultaneously at the falling edge of the sample/hold pulse. the sample/hold pulse width can be programmed to be 1 adc clock wide (minimum) or 16 adc clocks wide (maximum). note: in simultaneous mode, the adcin channel pair select has to be a0/b0, a1/b1, ..., a7/b7, and not in other combinations (such as a1/b3, etc.). analog input on channel ax analog input on channel bv adc clock sample and hold sh pulse t sh t dscha0_n t dschb0_n t dschb0_n+1 sample n sample n+1 sample n+2 t dscha0_n+1 t d(sh) adc event trigger from ev or other sources smode bit figure 6?41. simultaneous sampling mode timing table 6?46. simultaneous sampling mode timing sample n sample n + 1 at 25-mhz adc clock, t c(adcclk) = 40 ns remarks t d(sh) delay time from event trigger to sampling 2.5t c(adcclk) t sh sample/hold width/ acquisition width (1 + acqps) * t c(adcclk) 40 ns with acqps = 0 acqps value = 0?15 adctrl1[8:11] t d(scha0_n) delay time for first result to appear in result register 4t c(adcclk) 160 ns t d(schb0_n) delay time for first result to appear in result register 5t c(adcclk) 200 ns t d(scha0_n+1) delay time for successive results to appear in result register (3 + acqps) * t c(adcclk) 120 ns t d(schb0_n+1) delay time for successive results to appear in result register (3 + acqps) * t c(adcclk) 120 ns electrical specifications 144 april 2001 ? revised december 2004 sprs174l 6.30.8 definitions of specifications and terminology integral nonlinearity integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. the point used as zero occurs 1/2 lsb before the first code transition. the full-scale point is defined as level 1/2 lsb beyond the last code transition. the deviation is measured from the center of each particular code to the true straight line between these two points. differential nonlinearity an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. a differential nonlinearity error of less than 1 lsb ensures no missing codes. zero offset the major carry transition should occur when the analog input is at zero volts. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the nominal full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. signal-to-noise ratio + distortion (sinad) sinad is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the number of bits. using the following formula, n ( sinad 1.76 ) 6.02 it is possible to get a measure of performance expressed as n, the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. electrical specifications 145 april 2001 ? revised december 2004 sprs174l 6.31 multichannel buffered serial port (mcbsp) timing 6.31.1 mcbsp transmit and receive timing table 6?47. mcbsp timing requirements ?? no. min max unit mcbsp module clock (clkg, clkx, clkr) range 1 khz mcbsp module clock (clkg, clkx, clkr) range 20 mhz mcbsp module cycle time (clkg, clkx, clkr) range 50 ns mcbsp module cycle time (clkg, clkx, clkr) range 1 ms m11 t c(ckrx) cycle time, clkr/x clkr/x ext 2p ns m12 t w(ckrx) pulse duration, clkr/x high or clkr/x low clkr/x ext p?7 ns m13 t r(ckrx) rise time, clkr/x clkr/x ext 7 ns m14 t f(ckrx) fall time, clkr/x clkr/x ext 7 ns m15 t su(frh-ckrl) setup time, external fsr high before clkr low clkr int 18 ns m15 t su(frh-ckrl) setup time, external fsr high before clkr low clkr ext 2 ns m16 t h(ckrl-frh) hold time, external fsr high after clkr low clkr int 0 ns m16 t h(ckrl-frh) hold time, external fsr high after clkr low clkr ext 6 ns m17 t su(drv-ckrl) setup time, dr valid before clkr low clkr int 18 ns m17 t su(drv-ckrl) setup time, dr valid before clkr low clkr ext 2 ns m18 t h(ckrl-drv) hold time, dr valid after clkr low clkr int 0 ns m18 t h(ckrl-drv) hold time, dr valid after clkr low clkr ext 6 ns m19 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx int 18 ns m19 t su(fxh-ckxl) setup time, external fsx high before clkx low clkx ext 2 ns m20 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx int 0 ns m20 t h(ckxl-fxh) hold time, external fsx high after clkx low clkx ext 6 ns ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? 2p = 1/clkg in ns. clkg is the output of sample rate generator mux. clkg = clksrg (1 clkgdv) . clksrg can be lspclk, clkx, clkr as source. clksrg (sysclkout/2). mcbsp performance is limited by i/o buffer switching speed. internal clock prescalers must be adjusted such that the mcbsp clock (clkg, clkx, clkr) speeds are not greater than the i/o buf fer speed limit (20 mhz). electrical specifications 146 april 2001 ? revised december 2004 sprs174l table 6?48. mcbsp switching characteristics ?? no. parameter min max unit m1 t c(ckrx) cycle time, clkr/x clkr/x int 2p ns m2 t w(ckrxh) pulse duration, clkr/x high clkr/x int d?5 d+5 ns m3 t w(ckrxl) pulse duration, clkr/x low clkr/x int c?5 c+5 ns m4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr int 0 4 ns m4 t d(ckrh-frv) delay time, clkr high to internal fsr valid clkr ext 3 27 ns m5 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx int 0 4 ns m5 t d(ckxh-fxv) delay time, clkx high to internal fsx valid clkx ext 3 27 ns m6 t dis(ckxh-dxhz) disable time, clkx high to dx high impedance clkx int 8 ns m6 t dis(ckxh-dxhz) disable time, clkx high to dx high impedance following last data bit clkx ext 14 ns delay time, clkx high to dx valid. clkx int 9 delay time, clkx high to dx valid. this applies to all bits except the first bit transmitted. clkx ext 28 m7 t dxena = 0 clkx int 8 ns m7 t d(ckxh-dxv) delay time, clkx high to dx valid dxena = 0 clkx ext 14 ns only applies to first bit transmitted when in data dxena = 1 clkx int p + 8 only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx ext p + 14 dxena = 0 clkx int 0 m8 t en(ckxh-dx) enable time, clkx high to dx driven dxena = 0 clkx ext 6 ns m8 t en(ckxh-dx) only applies to first bit transmitted when in data dxena = 1 clkx int p ns only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes dxena = 1 clkx ext p + 6 dxena = 0 fsx int 8 m9 t d(fxh-dxv) delay time, fsx high to dx valid dxena = 0 fsx ext 14 ns m9 t d(fxh-dxv) only applies to first bit transmitted when in data dxena = 1 fsx int p + 8 ns only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode. dxena = 1 fsx ext p + 14 dxena = 0 fsx int 0 m10 t en(fxh-dx) enable time, fsx high to dx driven dxena = 0 fsx ext 6 ns m10 t en(fxh-dx) only applies to first bit transmitted when in data dxena = 1 fsx int p ns only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode dxena = 1 fsx ext p + 6 ? polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. ? 2p = 1/clkg in ns. c=clkrx low pulse width = p d=clkrx high pulse width = p electrical specifications 147 april 2001 ? revised december 2004 sprs174l (n?2) bit (n?1) (n?3) (n?2) bit (n?1) (n?4) (n?3) (n?2) bit (n?1) m18 m17 m18 m17 m17 m18 m16 m15 m4 m4 m14 m13 m3, m12 m1, m11 m2, m12 (rdatdly=10b) dr (rdatdly=01b) dr (rdatdly=00b) dr fsr (ext) fsr (int) clkr figure 6?42. mcbsp receive timing m8 m7 m7 m8 m6 m7 m9 m10 (xdatdly=10b) dx (xdatdly=01b) dx (xdatdly=00b) dx (n?2) bit (n?1) bit 0 (n?4) bit (n?1) (n?3) (n?2) bit 0 (n?3) (n?2) bit (n?1) bit 0 m20 m14 m13 m3, m12 m1, m11 m2, m12 fsx (ext) fsx (int) clkx m5 m5 m19 figure 6?43. mcbsp transmit timing electrical specifications 148 april 2001 ? revised december 2004 sprs174l 6.31.2 mcbsp as spi master or slave timing table 6?49. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 0) no. master slave unit no. min max min max unit m30 t su(drv-ckxl) setup time, dr valid before clkx low p?10 8p?10 ns m31 t h(ckxl-drv) hold time, dr valid after clkx low p?10 8p?10 ns m32 t su(bfxl-ckxh) setup time, fsx low before clkx high 8p+10 ns m33 t c(ckx) cycle time, clkx 2p 16p ns table 6?50. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 0) ? no. parameter master slave unit no. parameter min max min max unit m24 t h(ckxl-fxl) hold time, fsx low after clkx low 2p ns m25 t d(fxl-ckxh) delay time, fsx low to clkx high p ns m28 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 6 6p + 6 ns m29 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns ? 2p = 1/clkg for all spi slave modes, clkx has to be minimum 8 clkg cycles. also clkg should be lspclk/2 by setting clksm = clkgdv = 1. with maximum lspclk speed of 75 mhz, clkx maximum frequency will be lspclk/16 , that is 4.5 mhz and p =13.3 ns. bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx m30 m31 dr m28 m24 m29 m25 lsb msb m32 m33 figure 6?44. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 electrical specifications 149 april 2001 ? revised december 2004 sprs174l table 6?51. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 0) ? no. master slave unit no. min max min max unit m39 t su(drv-ckxh) setup time, dr valid before clkx high p?10 8p?10 ns m40 t h(ckxh-drv) hold time, dr valid after clkx high p?10 8p?10 ns m41 t su(fxl-ckxh) setup time, fsx low before clkx high 16p+10 ns m42 t c(ckx) cycle time, clkx 2p 16p ns table 6?52. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 0) ? no. parameter master slave unit no. parameter min max min max unit m34 t h(ckxl-fxl) hold time, fsx low after clkx low p ns m35 t d(fxl-ckxh) delay time, fsx low to clkx high 2p ns m37 t dis(ckxl-dxhz) disable time, dx high impedance following last data bit from clkx low p + 6 7p+6 ns m38 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns ? 2p = 1/clkg for all spi slave modes, clkx has to be minimum 8 clkg cycles. also clkg should be lspclk/2 by setting clksm = clkgdv = 1. with maximum lspclk speed of 75 mhz, clkx maximum frequency will be lspclk/16 , that is 4.5 mhz and p =13.3 ns. bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m35 m37 m40 m39 m38 m34 lsb msb m41 m42 figure 6?45. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 electrical specifications 150 april 2001 ? revised december 2004 sprs174l table 6?53. mcbsp as spi master or slave timing requirements (clkstp = 10b, clkxp = 1) ? no. master slave unit no. min max min max unit m49 t su(drv-ckxh) setup time, dr valid before clkx high p?10 8p?10 ns m50 t h(ckxh-drv) hold time, dr valid after clkx high p?10 8p?10 ns m51 t su(fxl-ckxl) setup time, fsx low before clkx low 8p+10 ns m52 t c(ckx) cycle time, clkx 2p 16p ns table 6?54. mcbsp as spi master or slave switching characteristics (clkstp = 10b, clkxp = 1) ? no. parameter master slave unit no. parameter min max min max unit m43 t h(ckxh-fxl) hold time, fsx low after clkx high 2p ns m44 t d(fxl-ckxl) delay time, fsx low to clkx low p ns m47 t dis(fxh-dxhz) disable time, dx high impedance following last data bit from fsx high 6 6p + 6 ns m48 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns ? 2p = 1/clkg for all spi slave modes, clkx has to be minimum 8 clkg cycles. also clkg should be lspclk/2 by setting clksm = clkgdv = 1. with maximum lspclk speed of 75 mhz, clkx maximum frequency will be lspclk/16 , that is 4.5 mhz and p =13.3 ns. m51 m50 m47 bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m44 m48 m49 m43 lsb msb m52 figure 6?46. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 electrical specifications 151 april 2001 ? revised december 2004 sprs174l table 6?55. mcbsp as spi master or slave timing requirements (clkstp = 11b, clkxp = 1) ? no. master slave unit no. min max min max unit m58 t su(drv-ckxl) setup time, dr valid before clkx low p ? 10 8p ? 10 ns m59 t h(ckxl-drv) hold time, dr valid after clkx low p ? 10 8p ? 10 ns m60 t su(fxl-ckxl) setup time, fsx low before clkx low 16p + 10 ns m61 t c(ckx) cycle time, clkx 2p 16p ns table 6?56. mcbsp as spi master or slave switching characteristics (clkstp = 11b, clkxp = 1) ? no. parameter master ? slave unit no. parameter min max min max unit m53 t h(ckxh-fxl) hold time, fsx low after clkx high p ns m54 t d(fxl-ckxl) delay time, fsx low to clkx low 2p ns m56 t dis(ckxh-dxhz) disable time, dx high impedance following last data bit from clkx high p+6 7p + 6 ns m57 t d(fxl-dxv) delay time, fsx low to dx valid 6 4p + 6 ns ? 2p = 1/clkg for all spi slave modes, clkx has to be minimum 8 clkg cycles. also clkg should be lspclk/2 by setting clksm = clkgdv = 1. with maximum lspclk speed of 75 mhz, clkx maximum frequency will be lspclk/16 , that is 4.5 mhz and p =13.3 ns. ? c = clkx low pulse width = p d = clkx high pulse width = p bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) clkx fsx dx dr m54 m58 m56 m53 m55 m59 m57 lsb msb m60 m61 figure 6?47. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 electrical specifications 152 april 2001 ? revised december 2004 sprs174l 6.32 flash timing (f281x only) 6.32.1 recommended operating conditions min nom max unit n f flash endurance for the array (write/erase cycles) 0 c to 85 c 100 1000 cycles n otp otp endurance for the array (write cycles) 0 c to 85 c 1 write table 6?57. flash parameters at 150-mhz sysclkout ? parameter min typ max unit 16-bit word 35 s program time 8k sector 170 ms program time 16k sector 320 ms erase time 8k sector 10 s erase time 16k sector 11 s i dd3vflp v dd3vfl current consumption during the erase/program cycle erase 75 ma i dd3vflp v dd3vfl current consumption during the erase/program cycle program 35 ma i ddp v dd current consumption during erase/program cycle 140 ma i ddiop v ddio current consumption during erase/program cycle 20 ma ? typical parameters as seen at room temperature using flash api v1 including function call overhead. table 6?58. flash/otp access timing parameter min max unit t a(fp) paged flash access time 36 ns t a(fr) random flash access time 36 ns t a(otp) otp access time 60 ns note: for 150 mhz, page ws = 5 and random ws = 5 for 135 mhz, page ws = 4 and random ws = 4 table 6?59. minimum required wait-states at different frequencies (f281x devices) sysclkout (mhz) sysclkout (ns) page wait-state ? random wait state ? 150 6.67 5 5 120 8.33 4 4 100 10 3 3 75 13.33 2 2 50 20 1 1 30 33.33 1 1 25 40 0 1 15 66.67 0 1 4 250 0 1 ? formulas to compute page wait state and random wait state: page wait state t a(fp) t c(sco) 1 (round up to the next highest integer), or 0 whichever is larger random wait state t a(fr) t c(sco) 1 (round up to the next highest integer), or 1 whichever is larger random wait state must be greater than or equal to 1 electrical specifications 153 april 2001 ? revised december 2004 sprs174l table 6?60. rom access timing parameter min max unit t a(rp) paged rom access time 23 ns t a(rr) random rom access time 23 ns t a(rom) rom (otp area) access time (see note 2) 60 ns notes: 1. for 150 mhz, page ws = 3 and random ws = 3 for 135 mhz, page ws = 3 and random ws = 3 2. in c281x devices, a 1k x 16 rom block replaces the otp block found in flash devices. table 6?61. minimum required wait-states at different frequencies (c281x devices) sysclkout (mhz) sysclkout (ns) page wait-state ? random wait state ? ? 150 6.67 3 3 120 8.33 2 2 100 10 2 2 75 13.33 1 1 50 20 1 1 30 33.33 0 1 25 40 0 1 15 66.67 0 1 4 250 0 1 ? formulas to compute page wait state and random wait state: page wait state t a(rp) t c(sco) 1 (round up to the next highest integer), or 0 whichever is larger random wait state t a(rr) t c(sco) 1 (round up to the next highest integer), or 1 whichever is larger ? random wait state must be greater than or equal to 1 electrical specifications 154 april 2001 ? revised december 2004 sprs174l 6.33 migrating from f281x devices to c281x devices the migration issues to be considered while migrating from the f281x devices to c281x devices are as follows: ? the 1k otp memory available in f281x devices has been replaced by 1k rom c281x devices. ? power sequencing is not needed for c281x devices. in other words, 3.3-v and 1.8-v (or 1.9-v) can ramp together. c281x can also be used on boards that have f281x power sequencing implemented; however, if the 1.8-v (or 1.9-v) rail lags the 3.3-v rail, the gpio pins are undefined until the 1.8-v rail reaches at least 1 v. ? current consumption differs for f281x and c281x devices for all four possible modes. see the appropriate electrical section for exact numbers. ? the v dd3vfl pin is the 3.3-v flash core power pin in f281x devices but is a v ddio pin in c281x devices. ? f281x and c281x devices are pin-compatible and code-compatible; however, they are electrically different with different emi/esd profiles. before ramping production with c281x devices, evaluate performance of the hardware design with both devices ? addresses 0x3d7bfc through 0x3d7bff in the otp and addresses 0x3f7ff2 through 0x3f7ff5 in the main rom array are reserved for rom part-specific information and are not available for user applications. ? the adc module in c281x devices can operate at 24.9k bias on adcresext pin for the full range 1?25mhz. while migrating the f281x designs to c281x, use a 24.9k resistor for biasing the adc. ? the paged and random wait-state specifications for the flash and rom parts are dif ferent. while migrating from flash to rom parts, the same wait-state values must be used for best performance compatibility (for example, in applications that use software delay loops or where precise interrupt latencies are critical). for errata applicable to 281x devices, see the tms320f2810, tms320f2811, tms320f2812, tms320c2810, tms320c2811, tms320c2812 digital signal processors silicon errata (literature number sprz193). mechanical data 155 april 2001 ? revised december 2004 sprs174l 7 mechanical data table 7?1 through table 7?4 provide the thermal resistance characteristics for the various packages. table 7?1. thermal resistance characteristics for 179-ball ghh parameter 179-ghh package unit psi jt 0.658 c/w ja 42.57 c/w jc 16.08 c/w table 7?2. thermal resistance characteristics for 179-ball zhh parameter 179-zhh package unit psi jt 0.658 c/w ja 42.57 c/w jc 16.08 c/w table 7?3. thermal resistance characteristics for 176-pin pgf parameter 176-pgf package unit psi jt 0.247 c/w ja 41.88 c/w jc 9.73 c/w table 7?4. thermal resistance characteristics for 128-pin pbk parameter 128-pbk package unit psi jt 0.271 c/w ja 41.65 c/w jc 10.76 c/w the following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s). packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) f741814apbl-1 active none call ti call ti tms320c2810 active none call ti call ti tms320f2810pbka active lqfp pbk 128 90 none cu nipdau level-2-220c-1yr tms320f2810pbkq active lqfp pbk 128 90 none cu nipdau level-2-220c-1yr tms320f2811pbka active lqfp pbk 128 90 none cu nipdau level-2-220c-1yr tms320f2811pbkq active lqfp pbk 128 90 none cu nipdau level-2-220c-1yr tms320f2812ghha active bga ghh 179 160 none call ti level-3-220c-168hr tms320f2812ghhar active bga ghh 179 1000 none call ti level-3-220c-168hr tms320f2812ghhq active bga ghh 179 160 none call ti level-3-220c-168hr TMS320F2812PGFA active lqfp pgf 176 40 none cu nipdau level-2-220c-1yr tms320f2812pgfq active lqfp pgf 176 40 none cu nipdau level-2-220c-1yr tms320f2812zhha active bga mi crosta r zhh 179 160 green (rohs & no sb/br) call ti level-3-260c-168hr tms320f2812zhhq active bga mi crosta r zhh 179 160 green (rohs & no sb/br) call ti level-3-260c-168hr tmx320f2812ghhs preview bga ghh 179 none call ti call ti tmx320f2812pgfs preview lqfp pgf 176 none call ti call ti (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 17-dec-2004 addendum-page 1 mechanical data mpbg058b ? january 1998 ? revised may 2002 1 post office box 655303 ? dallas, texas 75265 ghh (s?pbga?n179) plastic ball grid array 0,08 0,10 1,40 max 0,85 0,55 0,45 0,45 0,35 0,95 11,90 12,10 sq 4173504-3/c 12/01 seating plane 7 b a 2 1 c d f e g 4 3 6 5 n k h j l m p 9 8 11 10 13 12 14 0,40 10,40 typ a1 corner bottom view 0,80 0,80 0,40 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar bga configuration. microstar bga is a trademark of texas instruments. mpbg349 - march 2003 tm microstar bga is a trademark of texas instruments mechanical data mtqf015a january 1995 revised december 1996 21 post office box 655303 ? dallas, texas 75265 post office box 1443 ? houston, texas 772511443 pbk (s-pqfp-g128) plastic quad flatpack 4040279-3 / c 11/96 64 33 gage plane 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min 0,23 65 32 96 1 12,40 typ 0,13 97 128 sq sq 13,80 16,20 15,80 1,60 max 1,45 1,35 14,20 0 7 0,08 0,40 m 0,07 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 mechanical data mtqf020a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pgf (s-pqfp-g176) plastic quad flatpack 0,13 nom 89 0,17 0,27 88 45 0,45 0,25 0,75 44 seating plane 0,05 min 4040134 / b 11/96 gage plane 132 133 176 sq 24,20 sq 25,80 26,20 23,80 21,50 sq 1 1,45 1,35 1,60 max m 0,08 0,50 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 |
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